公开(公告)号：US20220037280A1

公开(公告)日：2022-02-03

申请号：US16941818

申请日：2020-07-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Naweed Anjum ,  Liang Wan ,  Michael Gerald Amaro

IPC: H01L23/00 ,  H01L23/58 ,  H01L23/498 ,  H01L21/56

Abstract: A semiconductor package includes a first layer including a semiconductor die embedded within a dielectric substrate, and a first set of metal pillars extending through the dielectric substrate, a second layer stacked on the first layer, the second layer including a metal trace patterned on the dielectric substrate of the first layer, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer, and a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars.

公开(公告)号：US20220028767A1

公开(公告)日：2022-01-27

申请号：US16940243

申请日：2020-07-27

Applicant: Texas Instruments Incorporated

Inventor： Naweed Anjum ,  Michael Gerald Amaro ,  Makarand Ramkrishna Kulkarni

IPC: H01L23/495 ,  H01L23/498

Abstract: A lead for a surface mount package for a semiconductor device, and the surface mount package employing the same. In one example, the lead includes a central segment with a first side and a second side, a first extension from a portion of the first side, and a second extension from a portion of the second side. The lead also includes a recess extending through a portion of the central segment, the first extension and the second extension.

公开(公告)号：US11587899B2

公开(公告)日：2023-02-21

申请号：US16941818

申请日：2020-07-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Naweed Anjum ,  Liang Wan ,  Michael Gerald Amaro

IPC: H01L21/44 ,  H01L23/52 ,  H01L23/00 ,  H01L23/58 ,  H01L23/498 ,  H01L21/56

Abstract: A semiconductor package includes a first layer including a semiconductor die embedded within a dielectric substrate, and a first set of metal pillars extending through the dielectric substrate, a second layer stacked on the first layer, the second layer including a metal trace patterned on the dielectric substrate of the first layer, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer, and a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars.

公开(公告)号：US11495549B2

公开(公告)日：2022-11-08

申请号：US17185589

申请日：2021-02-25

Applicant: Texas Instruments Incorporated

Inventor： Naweed Anjum ,  Michael Gerald Amaro ,  Charles Allen Devries, Jr.

IPC: H05K1/18 ,  H01L23/00 ,  H01L23/495

Abstract: A packaged electronic device includes a multilayer lead frame with first and second trace levels, a via level, an insulator, a conductive landing pad and a conductive crack arrest structure, the conductive landing pad has a straight profile that extends along a first direction along a side of the multilayer lead frame, the conductive crack arrest structure has a straight profile along the first direction and the conductive crack arrest structure is spaced from the conductive landing pad along an orthogonal second direction.

公开(公告)号：US11798900B2

公开(公告)日：2023-10-24

申请号：US17806694

申请日：2022-06-13

Applicant: Texas Instruments Incorporated

Inventor： Naweed Anjum ,  Michael Gerald Amaro ,  Charles Allen Devries, Jr.

IPC: H05K1/02 ,  H01L23/00 ,  H01L23/495 ,  H05K1/18

CPC classification number: H01L23/562 ,  H01L23/49503 ,  H01L23/49534 ,  H01L23/49541 ,  H05K1/181 ,  H05K2201/1003 ,  H05K2201/10015

Abstract: A packaged electronic device includes a multilayer lead frame with first and second trace levels, a via level, an insulator, a conductive landing pad and a conductive crack arrest structure, the conductive landing pad has a straight profile that extends along a first direction along a side of the multilayer lead frame, the conductive crack arrest structure has a straight profile along the first direction and the conductive crack arrest structure is spaced from the conductive landing pad along an orthogonal second direction.

公开(公告)号：US20220270984A1

公开(公告)日：2022-08-25

申请号：US17185589

申请日：2021-02-25

Applicant: Texas Instruments Incorporated

Inventor： Naweed Anjum ,  Michael Gerald Amaro ,  Charles Allen Devries, JR.

IPC: H01L23/00 ,  H01L23/495 ,  H05K1/18

Abstract: A packaged electronic device includes a multilayer lead frame with first and second trace levels, a via level, an insulator, a conductive landing pad and a conductive crack arrest structure, the conductive landing pad has a straight profile that extends along a first direction along a side of the multilayer lead frame, the conductive crack arrest structure has a straight profile along the first direction and the conductive crack arrest structure is spaced from the conductive landing pad along an orthogonal second direction.

公开(公告)号：US20240071889A1

公开(公告)日：2024-02-29

申请号：US17897974

申请日：2022-08-29

Applicant: Texas Instruments Incorporated

Inventor： Naweed Anjum ,  Michael Gerald Amaro ,  Makarand Ramkrishna Kulkarni

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/49805 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48245 ,  H01L2224/73265

Abstract: A lead for a surface mount package for a semiconductor device, and the surface mount package employing the same. In one example, the lead includes a central segment with a first side and a second side, a first extension from a portion of the first side, and a second extension from a portion of the second side. The lead also includes a recess extending through a portion of the central segment, the first extension and the second extension.

公开(公告)号：US20230207509A1

公开(公告)日：2023-06-29

申请号：US18171028

申请日：2023-02-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Naweed Anjum ,  Liang Wan ,  Michael Gerald Amaro

IPC: H01L23/00 ,  H01L23/58 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L24/24 ,  H01L21/568 ,  H01L23/58 ,  H01L23/49861 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/24195 ,  H01L2224/24227 ,  H01L2224/24265 ,  H01L2224/32227 ,  H01L2224/82005 ,  H01L2224/82101 ,  H01L2224/92244

Abstract: A semiconductor package includes a first layer including a semiconductor die embedded within a dielectric substrate, and a first set of metal pillars extending through the dielectric substrate, a second layer stacked on the first layer, the second layer including a metal trace patterned on the dielectric substrate of the first layer, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer, and a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars.

公开(公告)号：US20220310535A1

公开(公告)日：2022-09-29

申请号：US17806694

申请日：2022-06-13

Applicant: Texas Instruments Incorporated

Inventor： Naweed Anjum ,  Michael Gerald Amaro ,  Charles Allen Devries

IPC: H01L23/00 ,  H01L23/495 ,  H05K1/18

Abstract: A packaged electronic device includes a multilayer lead frame with first and second trace levels, a via level, an insulator, a conductive landing pad and a conductive crack arrest structure, the conductive landing pad has a straight profile that extends along a first direction along a side of the multilayer lead frame, the conductive crack arrest structure has a straight profile along the first direction and the conductive crack arrest structure is spaced from the conductive landing pad along an orthogonal second direction.

公开(公告)号：US11430720B2

公开(公告)日：2022-08-30

申请号：US16940243

申请日：2020-07-27

Applicant: Texas Instruments Incorporated

Inventor： Naweed Anjum ,  Michael Gerald Amaro ,  Makarand Ramkrishna Kulkarni

IPC: H01L23/495 ,  H01L23/498

Abstract: A lead for a surface mount package for a semiconductor device, and the surface mount package employing the same. In one example, the lead includes a central segment with a first side and a second side, a first extension from a portion of the first side, and a second extension from a portion of the second side. The lead also includes a recess extending through a portion of the central segment, the first extension and the second extension.