ANALOG-TO-DIGITAL CONVERTER (ADC) HAVING SELECTIVE COMPARATOR OFFSET ERROR TRACKING AND RELATED CORRECTIONS

    公开(公告)号:US20240259029A1

    公开(公告)日:2024-08-01

    申请号:US18629230

    申请日:2024-04-08

    CPC classification number: H03M1/1014

    Abstract: An analog-to-digital converter (ADC) includes: a set of comparators configured to provide comparison results based on an analog signal and respective reference thresholds for comparators of the set of comparators; digitization circuitry configured to provide a digital output code based on the comparison results and a mapping; and calibration circuitry. The calibration circuitry is configured to: receive the comparison results; determine if the analog signal is proximate to one of the respective reference thresholds based on the comparison results; in response to determining the analog signal is proximate to one of the respective reference thresholds, receive ADC values based on different pseudorandom binary sequence (PRBS) values being applied to the analog signal; determine an offset error based on the ADC values; and provide a comparator input offset calibration signal at a calibration circuitry output if the estimated offset error is greater than an offset error threshold.

    ANALOG-TO-DIGITAL CONVERTOR PSEUDO PERIODIC IL ESTIMATION

    公开(公告)号:US20230033830A1

    公开(公告)日:2023-02-02

    申请号:US17390362

    申请日:2021-07-30

    Abstract: Aspects of the description provide for an analog-to-digital converter (ADC) operable to convert an analog input signal to an output signal at an output of the ADC. In some examples, the ADC includes multiple sub-ADCs coupled in parallel, each of the multiple sub-ADCs coupled to the output of the ADC and operable to receive the analog input signal. The ADC is configured to operate the sub-ADCs in a consecutive operation loop including a transition phase in which the ADC operates each of the sub-ADCs sequentially for a first number of sequences, an estimation phase in which the ADC operates each of the sub-ADCs sequentially for a second number of sequences following the first number of sequences, and a randomization phase in which the ADC operates subsets of the sub-ADCs for a third number of sequences following the second number of sequences.

    ANALOG-TO-DIGITAL CONVERTER (ADC) HAVING SELECTIVE COMPARATOR OFFSET ERROR TRACKING AND RELATED CORRECTIONS

    公开(公告)号:US20230387933A1

    公开(公告)日:2023-11-30

    申请号:US17828967

    申请日:2022-05-31

    CPC classification number: H03M1/1014

    Abstract: An analog-to-digital converter (ADC) includes: a set of comparators configured to provide comparison results based on an analog signal and respective reference thresholds for comparators of the set of comparators; digitization circuitry configured to provide a digital output code based on the comparison results and a mapping; and calibration circuitry. The calibration circuitry is configured to: receive the comparison results; determine if the analog signal is proximate to one of the respective reference thresholds based on the comparison results; in response to determining the analog signal is proximate to one of the respective reference thresholds, receive ADC values based on different pseudorandom binary sequence (PRBS) values being applied to the analog signal; determine an offset error based on the ADC values; and provide a comparator input offset calibration signal at a calibration circuitry output if the estimated offset error is greater than an offset error threshold.

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