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    IQ MISMATCH CORRECTION FILTER
    1.
    发明申请
    IQ MISMATCH CORRECTION FILTER 审中-公开

    公开(公告)号：US20200153675A1

    公开(公告)日：2020-05-14

    申请号：US16525103

    申请日：2019-07-29

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sthanunathan RAMAKRISHNAN ,  Chandrasekhar SRIRAM ,  Raju Kharataram CHAUDHARI

    IPC: H04L27/36 ,  H04L27/38 ,  H04B1/30 ,  H03D3/00

    Abstract: An IQ estimation module comprising a powerup state IQ estimator configured to generate powerup state IQ estimates based on a powerup calibration of the IQ estimation module, a steady state IQ estimator configured to generate steady state IQ estimates during a steady state operation of the IQ estimation module, and an IQ estimate extender configured to determine differences between the powerup state IQ estimates and steady state IQ estimates at their respective frequency bins and adjust the powerup state IQ estimates to improve the accuracy of IQ estimates.

    CONTINUOUS TRACKING OF MISMATCH CORRECTION IN BOTH ANALOG AND DIGITAL DOMAINS IN AN INTERLEAVED ADC
    2.
    发明申请
    CONTINUOUS TRACKING OF MISMATCH CORRECTION IN BOTH ANALOG AND DIGITAL DOMAINS IN AN INTERLEAVED ADC 有权
    连续跟踪在交互式ADC中的两个模拟和数字域中的错误纠正

    公开(公告)号：US20170041011A1

    公开(公告)日：2017-02-09

    申请号：US15230643

    申请日：2016-08-08

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sashidharan VENKATRAMAN ,  Sthanunathan RAMAKRISHNAN ,  Jaiganesh BALAKRISHNAN

    IPC: H03M1/06 ,  H03M1/12

    CPC classification number: H03M1/0624 ,  H03M1/0626 ,  H03M1/1009 ,  H03M1/1215

    Abstract: A system. The system includes a first tracking filter configured to track a frequency domain mismatch profile between component analog-to-digital convertors (ADCs) of an interleaved ADC (IADC), and a second tracking filter configured to a track a frequency independent timing delay mismatch and a timing delay mismatch correction error based on frequency domain mismatch profile estimates. An output of the first tracking filter determines a correction of a frequency dependent mismatch profile in an output of the interleaved ADC and an output of the second tracking filter determines a correction of the timing delay mismatch correction error in the output of the interleaved ADC.

    Abstract translation: 一个系统。 该系统包括：第一跟踪滤波器，被配置为跟踪交织ADC（IADC）的分量模数转换器（ADC）之间的频域失配曲线;以及第二跟踪滤波器，其被配置为跟踪频率无关的定时延迟失配， 基于频域不匹配曲线估计的定时延迟失配校正误差。 第一跟踪滤波器的输出确定交错ADC的输出中的与频率相关的不匹配曲线的校正，并且第二跟踪滤波器的输出确定交错ADC的输出中的定时延迟失配校正误差的校正。

    ANALOG-TO-DIGITAL CONVERTOR PSEUDO PERIODIC IL ESTIMATION
    3.
    发明申请
    ANALOG-TO-DIGITAL CONVERTOR PSEUDO PERIODIC IL ESTIMATION 有权

    公开(公告)号：US20230033830A1

    公开(公告)日：2023-02-02

    申请号：US17390362

    申请日：2021-07-30

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sthanunathan RAMAKRISHNAN ,  Nithin GOPINATH ,  Sai Aditya NURANI ,  Joseph Palackal MATHEW ,  Nagalinga Swamy Basayya AREMALLAPUR

    IPC: H03M1/06

    Abstract: Aspects of the description provide for an analog-to-digital converter (ADC) operable to convert an analog input signal to an output signal at an output of the ADC. In some examples, the ADC includes multiple sub-ADCs coupled in parallel, each of the multiple sub-ADCs coupled to the output of the ADC and operable to receive the analog input signal. The ADC is configured to operate the sub-ADCs in a consecutive operation loop including a transition phase in which the ADC operates each of the sub-ADCs sequentially for a first number of sequences, an estimation phase in which the ADC operates each of the sub-ADCs sequentially for a second number of sequences following the first number of sequences, and a randomization phase in which the ADC operates subsets of the sub-ADCs for a third number of sequences following the second number of sequences.

    BAND SPECIFIC INTERLEAVING MISMATCH COMPENSATION IN RF ADCS
    5.
    发明申请
    BAND SPECIFIC INTERLEAVING MISMATCH COMPENSATION IN RF ADCS 审中-公开

    公开(公告)号：US20180175873A1

    公开(公告)日：2018-06-21

    申请号：US15791538

    申请日：2017-10-24

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sthanunathan RAMAKRISHNAN ,  Sashidharan VENKATRAMAN ,  Chandrasekhar SRIRAM ,  Jawaharlal TANGUDU

    IPC: H03M1/08 ,  H03M1/10

    CPC classification number: H03M1/08 ,  H03M1/1009 ,  H03M1/1042 ,  H03M1/1215

    Abstract: An integrated circuit chip includes an interleaved analog-to-digital converter (ADC) and an interleaving calibration circuit. The interleaved ADC includes a plurality of ADCs that are each configured to sample an analog signal. The interleaved ADC is configured to convert the analog signal into an interleaved analog-to-digital signal (IADC signal) that includes a plurality of spurious signals formed from mismatches between the plurality of ADCs. The interleaving calibration circuit is configured to receive the IADC signal from the interleaved ADC, generate a mismatch profile estimate corresponding to the plurality of spurious signals to generate one or more mismatch profile estimates, determine whether a first mismatch profile estimate is in a frequency band of interest, and, in response to a determination that the first mismatch profile estimate is in the frequency band of interest, generate a set of model parameters based on the first mismatch profile estimate.

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