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公开(公告)号：US20190273601A1
公开(公告)日：2019-09-05
申请号：US16417827
申请日：2019-05-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jaiganesh BALAKRISHNAN , Shagun DUSAD , Visvesvaraya PENTAKOTA , Srinivas Kumar Reddy NARU , Sarma Sundareswara GUNTURI , Nagalinga Swamy Basayya AREMALLAPUR
Abstract: A clock divider comprises a clock delay line that comprises a plurality of delay elements, a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements and a bit pattern source coupled to the clock delay selector. The clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.
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公开(公告)号：US20220173947A1
公开(公告)日：2022-06-02
申请号：US17538460
申请日：2021-11-30
Applicant: Texas Instruments Incorporated
IPC: H04L27/14
Abstract: A digital down converter (DDC) that improves efficiency by taking advantage of the periodicity of the coarse mixing process and the memory inherent in the convolution operation performed by decimation filters. In embodiments, the DDC filters and decimates a received signal to generate subfilter outputs and coarse mixes the subfilter outputs for each frequency band of interest. Accordingly, the DDC eliminates the need for separate decimation filters for each of the in-phase (I-phase) and quadrature (Q-phase) signals of each frequency band. In some embodiments, for each frequency band, the DDC combines the subfilter outputs into partial sums for each of the I- and Q-phases. In some of those embodiments, the coarse mixing operation is performed by multiplying the partial sums by real multiplicands and performing a simple post-rotation operation. In those embodiments, the DDC significantly reduces the number of multiplication operations required to perform the coarse mixing process.
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公开(公告)号：US20230033830A1
公开(公告)日：2023-02-02
申请号：US17390362
申请日：2021-07-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sthanunathan RAMAKRISHNAN , Nithin GOPINATH , Sai Aditya NURANI , Joseph Palackal MATHEW , Nagalinga Swamy Basayya AREMALLAPUR
IPC: H03M1/06
Abstract: Aspects of the description provide for an analog-to-digital converter (ADC) operable to convert an analog input signal to an output signal at an output of the ADC. In some examples, the ADC includes multiple sub-ADCs coupled in parallel, each of the multiple sub-ADCs coupled to the output of the ADC and operable to receive the analog input signal. The ADC is configured to operate the sub-ADCs in a consecutive operation loop including a transition phase in which the ADC operates each of the sub-ADCs sequentially for a first number of sequences, an estimation phase in which the ADC operates each of the sub-ADCs sequentially for a second number of sequences following the first number of sequences, and a randomization phase in which the ADC operates subsets of the sub-ADCs for a third number of sequences following the second number of sequences.
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公开(公告)号：US20210075368A1
公开(公告)日：2021-03-11
申请号：US16953666
申请日：2020-11-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: A phase coherent NCO circuit includes a base frequency NCO, a phase seeding circuit, a scaled frequency NCO, a sine/cosine generator. The base frequency NCO is configured to generate base phase values based on a base frequency control word. The phase seeding circuit is coupled to the base frequency NCO. The phase seeding circuit is configured to generate a seed phase value based on the base phase values and a scale factor value. The scaled frequency NCO is coupled to the phase seeding circuit. The scaled frequency NCO is configured to generate oscillator phase values based on the phase seed value and an oscillator frequency control word. The sine/cosine generator is coupled to the scaled frequency NCO. The sine/cosine generator is configured to generate oscillator output samples based on the oscillator phase values.
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Patent Agency Ranking
公开(公告)号：US20220182098A1
公开(公告)日：2022-06-09
申请号：US17544795
申请日：2021-12-07
Applicant: Texas Instruments Incorporated
Inventor： Sundarrajan RANGACHARI , Nagalinga Swamy Basayya AREMALLAPUR , Kalyan GUDIPATI , Divyeshkumar Mahendrabhai PATEL , Venkateshwara Reddy POTHAPU , Aravind VIJAYAKUMAR , Sarma Sundareswara GUNTURI , Jaiganesh BALAKRISHNAN
Abstract: A technique for reinitializing a coupled circuit, the technique including receiving a common configuration value associated with states of a coupled circuit, tracking states associated with the coupled circuit while the coupled circuit is in a low power state based on the common configuration value, receiving the tracked state associated with the coupled circuit, receiving a scaling value associated with the coupled circuit, determining a current state of the coupled circuit based on the tracked state and the scaling value, and transmitting an indication of the current state to the coupled circuit when the coupled circuit has exited the low power state.
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公开(公告)号：US20200212844A1
公开(公告)日：2020-07-02
申请号：US16403777
申请日：2019-05-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: A phase coherent NCO circuit includes a base frequency NCO, a phase seeding circuit, a scaled frequency NCO, a sine/cosine generator. The base frequency NCO is configured to generate base phase values based on a base frequency control word. The phase seeding circuit is coupled to the base frequency NCO. The phase seeding circuit is configured to generate a seed phase value based on the base phase values and a scale factor value. The scaled frequency NCO is coupled to the phase seeding circuit. The scaled frequency NCO is configured to generate oscillator phase values based on the phase seed value and an oscillator frequency control word. The sine/cosine generator is coupled to the scaled frequency NCO. The sine/cosine generator is configured to generate oscillator output samples based on the oscillator phase values.
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公开(公告)号：US20220066975A1
公开(公告)日：2022-03-03
申请号：US17364672
申请日：2021-06-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Aravind GANESAN , Nagalinga Swamy Basayya AREMALLAPUR , Jaiganesh BALAKRISHNAN , Robert Clair KELLER
Abstract: A circuit includes: a parallel data interface; and transition control circuitry coupled to the parallel data interface. The transition control circuitry is configured to: receive an input bit stream sample; determine a bit transformation pattern for the input bit stream sample in accordance with a target criteria; and generate an output bit stream symbol from the input bit stream sample and the bit transformation pattern, wherein the output bit stream symbol has more bits than the input bit stream sample.
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公开(公告)号：US20200177170A1
公开(公告)日：2020-06-04
申请号：US16281622
申请日：2019-02-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: A clock generator circuit includes a clock divider circuit, a clock pulse control circuit, a phase shifter circuit, and a clock multiplexer circuit. The clock divider circuit is configured to generate a divided clock having a frequency that is a programmable fraction of a frequency of an input clock. The clock pulse control circuit is coupled to the clock divider circuit, and is configured to generate a pulse shaped clock that includes a clock burst comprising a programmable number of adjacent cycles of the divided clock. The phase shifter circuit is coupled to the clock control circuit, and is configured to generate a plurality of phase shifted clocks. Each of phase shifted clocks is a differently delayed version of the pulse shaped clock. The clock multiplexer circuit is coupled to the phase shifter circuit, and is configured to selectively route each of the phase shifted clocks to an output terminal.
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公开(公告)号：US20200177168A1
公开(公告)日：2020-06-04
申请号：US16396873
申请日：2019-04-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Nagalinga Swamy Basayya AREMALLAPUR , Eeshan MIGLANI , Visvesvaraya PENTAKOTA , Praxal Sunilkumar SHAH
Abstract: A spur cancellation circuit for use in a mixed signal circuit. A spur cancellation circuit includes a clock generation circuit, a flip-flop bank, and a control circuit. The clock generation circuit is configured to generate a clock signal. The flip-flop bank is coupled to the clock generation circuit, and includes a plurality of flip-flops configured to be clocked by the clock signal. The control circuit is coupled to the clock generation circuit and the flip-flop bank. The control circuit is configured to individually enable one or more of the flip-flops to change state responsive to the clock signal and consume a predetermined amount of power; and to provide a data value to be clocked into the flip-flops.
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