公开(公告)号：US20220209782A1

公开(公告)日：2022-06-30

申请号：US17133745

申请日：2020-12-24

Applicant: Texas Instruments Incorporated

Inventor： Narasimhan RAJAGOPAL ,  Chirag Chandrahas SHETTY ,  Neeraj SHRIVASTAVA ,  Prasanth K ,  Eeshan MIGLANI

IPC: H03M1/12 ,  H03L7/081 ,  H03K5/24

Abstract: A method of using an analog-to-digital converter system includes receiving a sampled voltage corresponding to one of an input voltage and a known voltage, causing preamplifiers to generate output signals based on the sampled voltage, generating first and second signals based on the output signals, causing a delay-resolving delay-to-digital backend to generate a single-bit digital signal representing an order of receipt of the first and second signals, and adjusting one or more of the preamplifiers based on the digital signal. The disclosure also relates to a system which includes a voltage-to-delay frontend and a delay-resolving backend, and to a method which includes causing a delay comparator to generate a single-bit digital signal representing an order of receipt of input signals, causing the comparator to transmit a residue delay signal to a succeeding comparator, and transmitting a signal to adjust one or more of the preamplifiers based on the digital signal.

公开(公告)号：US20240372557A1

公开(公告)日：2024-11-07

申请号：US18772635

申请日：2024-07-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Narasimhan RAJAGOPAL ,  Nithin GOPINATH ,  Viswanathan NAGARAJAN ,  Neeraj SHRIVASTAVA ,  Visvesvaraya A. PENTAKOTA ,  Harshit MOONDRA ,  Abhinav CHANDRA

IPC: H03M1/10

Abstract: A circuit includes a nonlinear analog-to-digital converter (ADC) configured to provide a first digital output based on an analog input signal. The circuit also includes a linearization circuit having a lookup table (LUT) memory configured to store initial calibration data. The linearization circuit is coupled to the nonlinear ADC and is configured to: determine updated calibration data based on the initial calibration data; replace the initial calibration data in the LUT memory with the updated calibration data; and provide a second digital output at a linearization circuit output of the linearization circuit based on the first digital output and the updated calibration data.

公开(公告)号：US20230387932A1

公开(公告)日：2023-11-30

申请号：US17825864

申请日：2022-05-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Narasimhan RAJAGOPAL ,  Nithin GOPINATH ,  Viswanathan NAGARAJAN ,  Neeraj SHRIVASTAVA ,  Visvesvaraya A. PENTAKOTA ,  Harshit MOONDRA ,  Abhinav CHANDRA

IPC: H03M1/10

CPC classification number: H03M1/1014

Abstract: A circuit includes a nonlinear analog-to-digital converter (ADC) configured to provide a first digital output based on an analog input signal. The circuit also includes a linearization circuit having a lookup table (LUT) memory configured to store initial calibration data. The linearization circuit is coupled to the nonlinear ADC and is configured to: determine updated calibration data based on the initial calibration data; replace the initial calibration data in the LUT memory with the updated calibration data; and provide a second digital output at a linearization circuit output of the linearization circuit based on the first digital output and the updated calibration data.

公开(公告)号：US20220190856A1

公开(公告)日：2022-06-16

申请号：US17689627

申请日：2022-03-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sarma Sundareswara GUNTURI ,  Jagannathan VENKATARAMAN ,  Jawaharlal TANGUDU ,  Narasimhan RAJAGOPAL ,  Eeshan MIGLANI

IPC: H04B1/10 ,  H04B1/40 ,  H03G3/30 ,  H04B1/12

Abstract: Techniques maintaining receiver reliability, including determining a present attenuation level for an attenuator, wherein the attenuation level is set by a gain controller, determining a relative reliability threshold based on the present attenuation level, receiving a radio frequency (RF) signal, determining a voltage level of the received RF signal, comparing the voltage level of the received RF signal to the relative reliability threshold to determine that a reliability condition exists, and overriding, in response to the determination that the reliability condition exists, the present attenuation level set by the gain controller with an override attenuation level based on the present attenuation level.

公开(公告)号：US20210175914A1

公开(公告)日：2021-06-10

申请号：US17112137

申请日：2020-12-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sarma Sundareswara GUNTURI ,  Jagannathan VENKATARAMAN ,  Jawaharlal TANGUDU ,  Narasimhan RAJAGOPAL ,  Eeshan MIGLANI

IPC: H04B1/10 ,  H04B1/40 ,  H04B1/12 ,  H03G3/30

Abstract: Techniques maintaining receiver reliability, including determining a present attenuation level for an attenuator, wherein the attenuation level is set by a gain controller, determining a relative reliability threshold based on the present attenuation level, receiving a radio frequency (RF) signal, determining a voltage level of the received RF signal, comparing the voltage level of the received RF signal to the relative reliability threshold to determine that a reliability condition exists, and overriding, in response to the determination that the reliability condition exists, the present attenuation level set by the gain controller with an override attenuation level based on the present attenuation level.

公开(公告)号：US20190280703A1

公开(公告)日：2019-09-12

申请号：US16249225

申请日：2019-01-16

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Kumar Reddy NARU ,  Narasimhan RAJAGOPAL ,  Shagun DUSAD ,  Viswanathan NAGARAJAN ,  Visvesvaraya Appala PENTAKOTA

IPC: H03M1/06 ,  H03M1/00 ,  H03M1/04

Abstract: In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.

公开(公告)号：US20190007071A1

公开(公告)日：2019-01-03

申请号：US16125826

申请日：2018-09-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Viswanathan NAGARAJAN ,  Srinivas Kumar Reddy NARU ,  Narasimhan RAJAGOPAL

IPC: H03M13/39 ,  H03M13/11 ,  H03M1/12 ,  H03M1/10

CPC classification number: H03M13/39 ,  H03M1/0641 ,  H03M1/1014 ,  H03M1/1245 ,  H03M1/164 ,  H03M13/1145

Abstract: A pipeline ADC comprising an ADC segment and a digital backend coupled to the ADC segment. In some examples the ADC is configured to receive an analog signal, generate a first partial digital code representing a first sample of the analog signal, and generate a second partial digital code representing a second sample of the analog signal. In some examples the digital backend is configured to receive the first and second partial digital codes from the ADC segment, generate a combined digital code based at least partially on the first and second partial digital codes, determine a gain error of the ADC segment based at least partially on a first correlation of a PRBS with a difference between the first and second partial digital codes, and apply a first correction to the combined digital code based at least partially on the gain error of the ADC segment.