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1.发明公开公开(公告)号：US20240259029A1
公开(公告)日：2024-08-01
申请号：US18629230
申请日：2024-04-08
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Viswanathan NAGARAJAN , Aniket DATTA , Nithin GOPINATH
IPC: H03M1/10
CPC classification number: H03M1/1014
Abstract: An analog-to-digital converter (ADC) includes: a set of comparators configured to provide comparison results based on an analog signal and respective reference thresholds for comparators of the set of comparators; digitization circuitry configured to provide a digital output code based on the comparison results and a mapping; and calibration circuitry. The calibration circuitry is configured to: receive the comparison results; determine if the analog signal is proximate to one of the respective reference thresholds based on the comparison results; in response to determining the analog signal is proximate to one of the respective reference thresholds, receive ADC values based on different pseudorandom binary sequence (PRBS) values being applied to the analog signal; determine an offset error based on the ADC values; and provide a comparator input offset calibration signal at a calibration circuitry output if the estimated offset error is greater than an offset error threshold.
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公开(公告)号：US20240372557A1
公开(公告)日：2024-11-07
申请号：US18772635
申请日：2024-07-15
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Narasimhan RAJAGOPAL , Nithin GOPINATH , Viswanathan NAGARAJAN , Neeraj SHRIVASTAVA , Visvesvaraya A. PENTAKOTA , Harshit MOONDRA , Abhinav CHANDRA
IPC: H03M1/10
Abstract: A circuit includes a nonlinear analog-to-digital converter (ADC) configured to provide a first digital output based on an analog input signal. The circuit also includes a linearization circuit having a lookup table (LUT) memory configured to store initial calibration data. The linearization circuit is coupled to the nonlinear ADC and is configured to: determine updated calibration data based on the initial calibration data; replace the initial calibration data in the LUT memory with the updated calibration data; and provide a second digital output at a linearization circuit output of the linearization circuit based on the first digital output and the updated calibration data.
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Patent Agency Ranking
3.发明公开公开(公告)号：US20230387933A1
公开(公告)日：2023-11-30
申请号：US17828967
申请日：2022-05-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Viswanathan NAGARAJAN , Aniket DATTA , Nithin GOPINATH
IPC: H03M1/10
CPC classification number: H03M1/1014
Abstract: An analog-to-digital converter (ADC) includes: a set of comparators configured to provide comparison results based on an analog signal and respective reference thresholds for comparators of the set of comparators; digitization circuitry configured to provide a digital output code based on the comparison results and a mapping; and calibration circuitry. The calibration circuitry is configured to: receive the comparison results; determine if the analog signal is proximate to one of the respective reference thresholds based on the comparison results; in response to determining the analog signal is proximate to one of the respective reference thresholds, receive ADC values based on different pseudorandom binary sequence (PRBS) values being applied to the analog signal; determine an offset error based on the ADC values; and provide a comparator input offset calibration signal at a calibration circuitry output if the estimated offset error is greater than an offset error threshold.
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公开(公告)号：US20230387932A1
公开(公告)日：2023-11-30
申请号：US17825864
申请日：2022-05-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Narasimhan RAJAGOPAL , Nithin GOPINATH , Viswanathan NAGARAJAN , Neeraj SHRIVASTAVA , Visvesvaraya A. PENTAKOTA , Harshit MOONDRA , Abhinav CHANDRA
IPC: H03M1/10
CPC classification number: H03M1/1014
Abstract: A circuit includes a nonlinear analog-to-digital converter (ADC) configured to provide a first digital output based on an analog input signal. The circuit also includes a linearization circuit having a lookup table (LUT) memory configured to store initial calibration data. The linearization circuit is coupled to the nonlinear ADC and is configured to: determine updated calibration data based on the initial calibration data; replace the initial calibration data in the LUT memory with the updated calibration data; and provide a second digital output at a linearization circuit output of the linearization circuit based on the first digital output and the updated calibration data.
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公开(公告)号：US20190280703A1
公开(公告)日：2019-09-12
申请号：US16249225
申请日：2019-01-16
Applicant: Texas Instruments Incorporated
Inventor： Srinivas Kumar Reddy NARU , Narasimhan RAJAGOPAL , Shagun DUSAD , Viswanathan NAGARAJAN , Visvesvaraya Appala PENTAKOTA
Abstract: In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.
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公开(公告)号：US20190007071A1
公开(公告)日：2019-01-03
申请号：US16125826
申请日：2018-09-10
Applicant: TEXAS INSTRUMENTS INCORPORATED
CPC classification number: H03M13/39 , H03M1/0641 , H03M1/1014 , H03M1/1245 , H03M1/164 , H03M13/1145
Abstract: A pipeline ADC comprising an ADC segment and a digital backend coupled to the ADC segment. In some examples the ADC is configured to receive an analog signal, generate a first partial digital code representing a first sample of the analog signal, and generate a second partial digital code representing a second sample of the analog signal. In some examples the digital backend is configured to receive the first and second partial digital codes from the ADC segment, generate a combined digital code based at least partially on the first and second partial digital codes, determine a gain error of the ADC segment based at least partially on a first correlation of a PRBS with a difference between the first and second partial digital codes, and apply a first correction to the combined digital code based at least partially on the gain error of the ADC segment.
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公开(公告)号：US20170041013A1
公开(公告)日：2017-02-09
申请号：US15231415
申请日：2016-08-08
Applicant: TEXAS INSTRUMENTS INCORPORATED
CPC classification number: H03M1/0641 , H03M1/168
Abstract: A system includes an analog-to-digital converter (ADC) including an ADC input terminal; an ADC output terminal; and analog components configured to convert an analog signal received at the ADC input terminal to a digital signal. The system also includes a histogram estimation circuit coupled to the ADC output terminal and configured to generate information on a plurality of codes generated by the ADC and determine a region defining a range of codes corresponding to an occurrence of an error caused by the analog components of the ADC. The system also includes a dither circuit coupled to the ADC input terminal and configured to introduce a dither in the analog signal to generate a modified analog signal.
Abstract translation: 系统包括包括ADC输入端的模数转换器（ADC）; 一个ADC输出端; 以及被配置为将在ADC输入端接收的模拟信号转换成数字信号的模拟部件。 该系统还包括耦合到ADC输出端并被配置为生成关于由ADC产生的多个代码的信息的直方图估计电路，并且确定一个区域，该区域对应于由模拟分量引起的误差的发生 ADC。 该系统还包括耦合到ADC输入端并被配置为在模拟信号中引入抖动以产生经修改的模拟信号的抖动电路。
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