公开(公告)号：US11916703B2

公开(公告)日：2024-02-27

申请号：US18066027

申请日：2022-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abishek Manian ,  Nithin Sathisan Poduval ,  Roland Nii Ofei Ribeiro

IPC: H04L25/03 ,  H03K3/037

CPC classification number: H04L25/03057 ,  H03K3/0372

Abstract: An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.

公开(公告)号：US12184279B2

公开(公告)日：2024-12-31

申请号：US18539381

申请日：2023-12-14

Applicant: Texas Instruments Incorporated

Inventor： Nithin Sathisan Poduval ,  Abishek Manian ,  Roland Nii Ofei Ribeiro

IPC: H03K19/0185 ,  H03K3/037

Abstract: An example apparatus includes: a first level shifting circuit including a supply output; a first deserializer stage including a supply input, a first input, a first output, and a second output, the supply input coupled to the supply output; a second level shifting circuit including a second input and a third output, the second input coupled to the first output; and a second deserializer stage including a third input, a fourth output and a fifth output, the third input coupled to the third output.

公开(公告)号：US20240113713A1

公开(公告)日：2024-04-04

申请号：US18539381

申请日：2023-12-14

Applicant: Texas Instruments Incorporated

Inventor： Nithin Sathisan Poduval ,  Abishek Manian ,  Roland Nii Ofei Ribeiro

IPC: H03K19/0185 ,  H03K3/037

CPC classification number: H03K19/018521 ,  H03K3/037

Abstract: An example apparatus includes: a first level shifting circuit including a supply output; a first deserializer stage including a supply input, a first input, a first output, and a second output, the supply input coupled to the supply output; a second level shifting circuit including a second input and a third output, the second input coupled to the first output; and a second deserializer stage including a third input, a fourth output and a fifth output, the third input coupled to the third output.

公开(公告)号：US11575546B2

公开(公告)日：2023-02-07

申请号：US17193067

申请日：2021-03-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abishek Manian ,  Nithin Sathisan Poduval ,  Roland Nii Ofei Ribeiro

IPC: H04L25/03 ,  H03K3/037

Abstract: An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.

公开(公告)号：US11888478B2

公开(公告)日：2024-01-30

申请号：US17515034

申请日：2021-10-29

Applicant: Texas Instruments Incorporated

Inventor： Nithin Sathisan Poduval ,  Abishek Manian ,  Roland Nii Ofei Ribeiro

IPC: H03K19/0185 ,  H03K3/037

CPC classification number: H03K19/018521 ,  H03K3/037

Abstract: An example apparatus includes: a first level shifting circuit including a supply output; a first deserializer stage including a supply input, a first input, a first output, and a second output, the supply input coupled to the supply output; a second level shifting circuit including a second input and a third output, the second input coupled to the first output; and a second deserializer stage including a third input, a fourth output and a fifth output, the third input coupled to the third output.

公开(公告)号：US20230135422A1

公开(公告)日：2023-05-04

申请号：US17515034

申请日：2021-10-29

Applicant: Texas Instruments Incorporated

Inventor： Nithin Sathisan Poduval ,  Abishek Manian ,  Roland Nii Ofei Ribeiro

IPC: H03K19/0185 ,  H03K3/037

Abstract: An example apparatus includes: a first level shifting circuit including a supply output; a first deserializer stage including a supply input, a first input, a first output, and a second output, the supply input coupled to the supply output; a second level shifting circuit including a second input and a third output, the second input coupled to the first output; and a second deserializer stage including a third input, a fourth output and a fifth output, the third input coupled to the third output.