-
公开(公告)号：US11323109B2
公开(公告)日：2022-05-03
申请号：US17084901
申请日：2020-10-30
摘要： A clockless delay adaptation loop configured to adapt to random data includes a first and a second delay line, an autocorrelator, and a controller. The autocorrelator receives an input signal for the delay adaptation loop and the output from the first delay line, and includes a first logic circuit configured to output a first autocorrelation and a second logic circuit configured to output a second autocorrelation. The controller is configured generate a control signal for one of the first and second delay lines based on the first and second autocorrelations. In some examples, the first logic circuit is an XNOR gate, and the second logic circuit is an OR gate. In some examples, the OR gate can have a gain that is two times a gain of the XNOR gate. In some examples, an amplifier having two times the gain of the XNOR gate is coupled to the OR gate.
-
公开(公告)号：US10484042B2
公开(公告)日：2019-11-19
申请号：US16118621
申请日：2018-08-31
发明人： Abishek Manian , Amit Rane
IPC分类号： H04B1/58 , H04L25/02 , H03K19/0175 , H03F3/45
摘要： A bidirectional data link includes a forward channel transmitter circuit and a forward channel receiver circuit. The forward channel transmitter circuit includes a forward channel driver circuit, and a back channel receiver circuit. The back channel receiver circuit is coupled to the forward channel driver circuit. The back channel receiver circuit includes a summation circuit and an active filter circuit. The summation circuit is coupled to the forward channel driver circuit. The active filter circuit is coupled to the summation circuit. The forward channel receiver circuit includes a forward channel receiver, and a back channel driver circuit. The back channel driver circuit is coupled to the forward channel receiver.
-
公开(公告)号：US11916703B2
公开(公告)日：2024-02-27
申请号：US18066027
申请日：2022-12-14
CPC分类号： H04L25/03057 , H03K3/0372
摘要： An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.
-
公开(公告)号：US10804956B2
公开(公告)日：2020-10-13
申请号：US16599377
申请日：2019-10-11
发明人： Abishek Manian , Amit Rane
IPC分类号： H04B1/58 , H04L25/02 , H03K19/0175 , H03F3/45
摘要： A bidirectional data link includes a forward channel transmitter circuit and a forward channel receiver circuit. The forward channel transmitter circuit includes a forward channel driver circuit, and a back channel receiver circuit. The back channel receiver circuit is coupled to the forward channel driver circuit. The back channel receiver circuit includes a summation circuit and an active filter circuit. The summation circuit is coupled to the forward channel driver circuit. The active filter circuit is coupled to the summation circuit. The forward channel receiver circuit includes a forward channel receiver, and a back channel driver circuit. The back channel driver circuit is coupled to the forward channel receiver.
-
公开(公告)号：US20240113713A1
公开(公告)日：2024-04-04
申请号：US18539381
申请日：2023-12-14
IPC分类号： H03K19/0185 , H03K3/037
CPC分类号： H03K19/018521 , H03K3/037
摘要： An example apparatus includes: a first level shifting circuit including a supply output; a first deserializer stage including a supply input, a first input, a first output, and a second output, the supply input coupled to the supply output; a second level shifting circuit including a second input and a third output, the second input coupled to the first output; and a second deserializer stage including a third input, a fourth output and a fifth output, the third input coupled to the third output.
-
公开(公告)号：US11575546B2
公开(公告)日：2023-02-07
申请号：US17193067
申请日：2021-03-05
摘要： An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.
-
公开(公告)号：US11539555B2
公开(公告)日：2022-12-27
申请号：US17095869
申请日：2020-11-12
摘要： An N-tap feedforward equalizer (FFE) comprises a set of N FFE taps coupled together in parallel, a filter coupled between the (N−1)th FFE tap and the Nth FFE tap, and a summer coupled to an output of the set of N FFE taps. Each FFE tap includes a unique sample-an-hold (S/H) circuit that generates a unique time-delayed signal and a unique transconductance stage that generates a unique transconductance output based on the unique time-delayed signal. The filter causes the N-tap FFE to have the behavior of greater than N taps. In some examples, the filter is a first order high pass filter that causes coefficients greater than N to have an opposite polarity of the Nth coefficient. In some examples, the filter is a first order low pass filter that causes coefficients greater than N to have the same polarity as the Nth coefficient.
-
公开(公告)号：US10608650B2
公开(公告)日：2020-03-31
申请号：US16002881
申请日：2018-06-07
摘要： In examples, a voltage-controlled oscillator (VCO) comprises an inductor; a first pair of transistors having first terminals coupled to a voltage source, second terminals coupled to opposing ends of the inductor, and control terminals coupled to opposing ends of the inductor; and a second pair of transistors having first terminals coupled to ground, second terminals coupled to opposing ends of the inductor, and control terminals coupled to opposing ends of the inductor. The VCO also comprises a first transistor coupled to at least one capacitor, the combination of the first transistor and the at least one capacitor coupled to the inductor in parallel. The VCO further comprises second, third, and fourth transistors coupled to a control terminal of the first transistor, the second transistor coupled to the voltage source, the fourth transistor coupled to ground, and the third transistor configured to receive a ramped voltage.
-
公开(公告)号：US11888478B2
公开(公告)日：2024-01-30
申请号：US17515034
申请日：2021-10-29
IPC分类号： H03K19/0185 , H03K3/037
CPC分类号： H03K19/018521 , H03K3/037
摘要： An example apparatus includes: a first level shifting circuit including a supply output; a first deserializer stage including a supply input, a first input, a first output, and a second output, the supply input coupled to the supply output; a second level shifting circuit including a second input and a third output, the second input coupled to the first output; and a second deserializer stage including a third input, a fourth output and a fifth output, the third input coupled to the third output.
-
公开(公告)号：US11743080B2
公开(公告)日：2023-08-29
申请号：US17083008
申请日：2020-10-28
CPC分类号： H04L27/01 , H04L25/03057 , H04L25/03343 , H04L25/03885 , H04L2025/0349
摘要： A linear retimer includes an equalizer, a clock recovery circuit, a sample and hold (S/H) circuit, and a linear driver. The equalizer receives an input signal and outputs an equalized signal. The clock recovery circuit receives the equalized signal and outputs a clock signal. The S/H circuit receives the equalized signal and the clock signal and outputs a retimed signal. The linear driver receives the retimed signal and outputs a recovered signal. The S/H circuit is configured to preserve a voltage of the equalized signal in the retimed signal. In some examples, the S/H circuit is part of a linear three-tap feedforward equalizer, and the linear driver receives an output of the feedforward equalizer. The linear retimer can be placed between a transmitter and a channel or after the channel.
-
-
-
-
-
-
-
-
-
搜索结果
17 条记录 (耗时 0.015 秒)
