REFERENCE PRECHARGE SYSTEM
    1.
    发明申请

    公开(公告)号:US20210391836A1

    公开(公告)日:2021-12-16

    申请号:US16903030

    申请日:2020-06-16

    Abstract: A precharge circuit comprises a gain amplifier, a comparator, a reservoir capacitor, a switch, a current source, and a switching network. The gain amplifier has a gain G1 and receives an input voltage Vrefp. The gain amplifier outputs an amplified voltage G1Vrefp to the comparator, which compares G1Vrefp to a voltage across the reservoir capacitor. The comparator outputs a control signal for the switch based on the comparison. The switch couples the current source to the reservoir capacitor. The current from the current source charges the reservoir capacitor. The switching network couples the reservoir capacitor to an output of the precharge circuit during a first operating mode and provides the input voltage Vrefp to the output during a second operating mode.

    MEASURING INTERNAL VOLTAGES OF PACKAGED ELECTRONIC DEVICES

    公开(公告)号:US20190121381A1

    公开(公告)日:2019-04-25

    申请号:US15973691

    申请日:2018-05-08

    CPC classification number: G05F3/16 G01R31/2884 G01R31/2896 H03M3/30

    Abstract: An method comprising activating an internal switch within a packaged electronic device to connect to a reference ground of an internal voltage source to a first input of an analog front end, receiving an external ground potential voltage at a first package pin of the packaged electronic device, generating a zero detector output signal for the packaged electronic device at a second package pin, activating the internal switch to connect the first input of the analog front end to the internal voltage source, receiving a second voltage level at the first package pin that generates a second output signal that matches the zero detector output signal, and receiving trim instructions to trim an internal voltage generated by the internal voltage source to a voltage level that is closer to a target voltage level.

    MEASURING INTERNAL VOLTAGES OF PACKAGED ELECTRONIC DEVICES

    公开(公告)号:US20200081473A1

    公开(公告)日:2020-03-12

    申请号:US16526801

    申请日:2019-07-30

    Abstract: An method comprising activating an internal switch within a packaged electronic device to connect to a reference ground of an internal voltage source to a first input of an analog front end, receiving an external ground potential voltage at a first package pin of the packaged electronic device, generating a zero detector output signal for the packaged electronic device at a second package pin, activating the internal switch to connect the first input of the analog front end to the internal voltage source, receiving a second voltage level at the first package pin that generates a second output signal that matches the zero detector output signal, and receiving trim instructions to trim an internal voltage generated by the internal voltage source to a voltage level that is closer to a target voltage level.

    MEASURING INTERNAL VOLTAGES OF PACKAGED ELECTRONIC DEVICES

    公开(公告)号:US20200319661A1

    公开(公告)日:2020-10-08

    申请号:US16908784

    申请日:2020-06-23

    Abstract: A method comprising activating an internal switch within a packaged electronic device to connect to a reference ground of an internal voltage source to a first input of an analog front end, receiving an external ground potential voltage at a first package pin of the packaged electronic device, generating a zero detector output signal for the packaged electronic device at a second package pin, activating the internal switch to connect the first input of the analog front end to the internal voltage source, receiving a second voltage level at the first package pin that generates a second output signal that matches the zero detector output signal, and receiving trim instructions to trim an internal voltage generated by the internal voltage source to a voltage level that is closer to a target voltage level.

    BURIED ZENER DIODE VOLTAGE REFERENCE WITH DIGITAL CORRECTION

    公开(公告)号:US20240288894A1

    公开(公告)日:2024-08-29

    申请号:US18175208

    申请日:2023-02-27

    CPC classification number: G05F3/18 G05F1/468

    Abstract: In an example, a system includes a buried Zener diode having a first terminal coupled to a voltage terminal. The system also includes a first resistor having a first terminal coupled to a second terminal of the buried Zener diode. The system includes a second resistor having a first terminal coupled to a second terminal of the first resistor. The system also includes a first transistor having a control terminal coupled to the first terminal of the second resistor. The system includes a second transistor having a control terminal coupled to a second terminal of the second resistor and an emitter coupled to an emitter of the first transistor. The system also includes a resistor network coupled to the second terminal of the first resistor, where the resistor network is configured to produce a reference voltage.

    DELTA SIGMA MODULATOR
    6.
    发明申请

    公开(公告)号:US20220109452A1

    公开(公告)日:2022-04-07

    申请号:US17061647

    申请日:2020-10-02

    Abstract: A delta-sigma modulator includes a first amplifier having an input, a feedback control input, and an output. The input is a first input of the delta-sigma modulator. The delta-sigma modulator further includes a first integrator and a first quantizer. The first integrator has an input and an output. The output of the first amplifier is coupled to the input of the first integrator. The first quantizer has an input and an output. The output of the first quantizer is coupled to the feedback control input of the first amplifier.

    SWITCHED-CAPACITOR FILTER WITH GLITCH REDUCTION

    公开(公告)号:US20190229709A1

    公开(公告)日:2019-07-25

    申请号:US16046581

    申请日:2018-07-26

    Abstract: An apparatus includes a switched-capacitor filter. The switched-capacitor filter includes an integrator and a feedback loop between an output node of the integrator and an input node of the integrator, wherein the feedback loop includes a feedback capacitor, a first switch, and a second switch. The switched-capacitor filter also includes a pre-charge path between the output node of the integrator and the feedback capacitor, wherein the pre-charge path includes a pre-charge buffer and a third switch.

    OPERATIONAL AMPLIFIER WITH CLASS AB OUTPUT
    8.
    发明申请
    OPERATIONAL AMPLIFIER WITH CLASS AB OUTPUT 有权
    具有AB类输出的操作放大器

    公开(公告)号:US20170040963A1

    公开(公告)日:2017-02-09

    申请号:US15229756

    申请日:2016-08-05

    CPC classification number: H03F3/211 H03F3/3022 H03F3/45192 H03F2203/45288

    Abstract: An operational amplifier includes an output stage, an input stage, a first auxiliary amplifier, and a second auxiliary amplifier. The output stage includes a first output transistor and a second output transistor. The input stage is configured to drive the output stage. The first auxiliary amplifier is coupled to an output of the input stage and to an input of the first output transistor. The first auxiliary amplifier is configured to bias the first output transistor for class AB operation and to isolate the input stage from a bias voltage applied to the first output transistor. The second auxiliary amplifier is coupled to the output of the input stage and to an input of the second output transistor. The second auxiliary amplifier is configured to bias the second output transistor for class AB operation, and to isolate the input stage from a bias voltage applied to the second output transistor.

    Abstract translation: 运算放大器包括输出级,输入级,第一辅助放大器和第二辅助放大器。 输出级包括第一输出晶体管和第二输出晶体管。 输入级配置为驱动输出级。 第一辅助放大器耦合到输入级的输出端和第一输出晶体管的输入端。 第一辅助放大器被配置为偏置用于AB类操作的第一输出晶体管,并且将输入级与施加到第一输出晶体管的偏置电压隔离。 第二辅助放大器耦合到输入级的输出端和第二输出晶体管的输入端。 第二辅助放大器被配置为偏置用于AB类操作的第二输出晶体管,并且将输入级与施加到第二输出晶体管的偏置电压隔离。

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