公开(公告)号：US20210210440A1

公开(公告)日：2021-07-08

申请号：US16737237

申请日：2020-01-08

Applicant: Texas Instruments Incorporated

Inventor： Christopher Daniel Manack ,  Qiao Chen ,  Michael Todd Wyant ,  Matthew John Sherbin ,  Patrick Francis Thompson

IPC: H01L23/58 ,  H01L23/532 ,  H01L23/528

Abstract: An integrated circuit (IC) die includes a substrate with circuitry configured for at least one function including metal interconnect levels thereon including a top metal interconnect level and a bottom metal interconnect level, with a passivation layer on the top metal interconnect level. A scribe street is around a periphery of the IC die, the scribe street including a scribe seal utilizing at least two of the plurality of metal interconnect levels, an inner metal meander stop ring including at least the top metal interconnect level located outside the scribe seal, wherein the scribe seal and the inner metal meander stop ring are separated by a first separation gap. An outer metal meander stop ring including at least the top metal interconnect level is located outside the inner metal stop ring, wherein the outer stop ring and the inner stop ring are separated by a second separation gap.

公开(公告)号：US12255115B2

公开(公告)日：2025-03-18

申请号：US18617517

申请日：2024-03-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christopher Daniel Manack ,  Patrick Francis Thompson ,  Qiao Chen

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/495

Abstract: In examples, a semiconductor device comprises a semiconductor package including a mold compound covering a semiconductor die. The semiconductor package has a surface and a cavity formed in the surface. The semiconductor device comprises an electronic device positioned within the cavity, the electronic device coupled to the semiconductor die via a conductive terminal extending through the mold compound.

公开(公告)号：US11942386B2

公开(公告)日：2024-03-26

申请号：US17001429

申请日：2020-08-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christopher Daniel Manack ,  Patrick Francis Thompson ,  Qiao Chen

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L23/315 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49575 ,  H01L24/02 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/48465 ,  H01L2224/73207 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/07025 ,  H01L2924/19104

Abstract: In examples, a semiconductor device comprises a semiconductor package including a mold compound covering a semiconductor die. The semiconductor package has a surface and a cavity formed in the surface. The semiconductor device comprises an electronic device positioned within the cavity, the electronic device coupled to the semiconductor die via a conductive terminal extending through the mold compound.

公开(公告)号：US12009319B2

公开(公告)日：2024-06-11

申请号：US16737237

申请日：2020-01-08

Applicant: Texas Instruments Incorporated

Inventor： Christopher Daniel Manack ,  Qiao Chen ,  Michael Todd Wyant ,  Matthew John Sherbin ,  Patrick Francis Thompson

IPC: H01L23/58 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/585 ,  H01L23/528 ,  H01L23/53209

Abstract: An integrated circuit (IC) die includes a substrate with circuitry configured for at least one function including metal interconnect levels thereon including a top metal interconnect level and a bottom metal interconnect level, with a passivation layer on the top metal interconnect level. A scribe street is around a periphery of the IC die, the scribe street including a scribe seal utilizing at least two of the plurality of metal interconnect levels, an inner metal meander stop ring including at least the top metal interconnect level located outside the scribe seal, wherein the scribe seal and the inner metal meander stop ring are separated by a first separation gap. An outer metal meander stop ring including at least the top metal interconnect level is located outside the inner metal stop ring, wherein the outer stop ring and the inner stop ring are separated by a second separation gap.

公开(公告)号：US11855024B2

公开(公告)日：2023-12-26

申请号：US17463047

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Qiao Chen ,  Vivek Swaminathan Sridharan ,  Christopher Daniel Manack ,  Patrick Francis Thompson ,  Jonathan Andrew Montoya ,  Salvatore Frank Pavone

IPC: H01L23/00

CPC classification number: H01L24/09 ,  H01L24/25 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/09181 ,  H01L2224/2541 ,  H01L2224/73209 ,  H01L2224/81801

Abstract: In some examples a wafer chip scale package (WCSP) includes a semiconductor die having a device side in which a circuit is formed, and a redistribution layer (RDL) coupled to the device side that is positioned within an insulating member. In addition, the WCSP includes a scribe seal circumscribing the circuit along the device side, wherein the RDL abuts the scribe seal. Further, the WCSP includes a conductive member coupled to the RDL. The conductive member is configured to receive a solder member, and the insulating member does not extend along the device side of the semiconductor die between the conductive member and a portion of an outer perimeter of the WCSP closest to the conductive member.