公开(公告)号：US12080697B2

公开(公告)日：2024-09-03

申请号：US17525533

申请日：2021-11-12

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Shiqi Huang ,  Wei Liu ,  Bater Chelon ,  Siping Hu

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/528 ,  H01L25/00 ,  H01L25/065 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L25/18 ,  H01L23/528 ,  H01L24/03 ,  H01L24/08 ,  H01L24/09 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27 ,  H10B43/40 ,  H01L2224/08112 ,  H01L2224/08146 ,  H01L2224/09181 ,  H01L2224/32147 ,  H01L2224/33181 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/14511

Abstract: Embodiments of bonded 3D memory devices and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a plurality of first NAND memory strings and a plurality of first BLs. At least one of the first BLs may be conductively connected to a respective one of the first NAND memory strings. The first semiconductor structure also includes a plurality of first conductor layers, and a first bonding layer having a plurality of first bit line bonding contacts conductively connected to the plurality of first BLs and a plurality of first word line bonding contacts conductively connected to the first conductor layers. A second semiconductor structure includes a plurality of second NAND memory strings and a plurality of second BLs.

公开(公告)号：US20240186284A1

公开(公告)日：2024-06-06

申请号：US18464982

申请日：2023-09-11

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Chandrasekhar Mandalapu ,  Gaius Gillman Fountain, JR. ,  Guilian Gao

IPC: H01L23/00 ,  H01L21/683 ,  H01L21/78

CPC classification number: H01L24/83 ,  H01L21/6836 ,  H01L21/78 ,  H01L24/03 ,  H01L24/08 ,  H01L24/09 ,  H01L24/32 ,  H01L24/33 ,  H01L24/98 ,  H01L2221/68327 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/80895 ,  H01L2224/83009 ,  H01L2224/83896 ,  H01L2224/83948

Abstract: Devices and techniques include process steps for preparing various microelectronic components for bonding, such as for direct bonding without adhesive. The processes include providing a first bonding surface on a first surface of the microelectronic components, bonding a handle to the prepared first bonding surface, and processing a second surface of the microelectronic components while the microelectronic components are gripped at the handle. In some embodiments, the processes include removing the handle from the first bonding surface, and directly bonding the microelectronic components at the first bonding surface to other microelectronic components.

公开(公告)号：US11769700B2

公开(公告)日：2023-09-26

申请号：US16997377

申请日：2020-08-19

Applicant: SK hynix Inc.

Inventor： Bok Gyu Min

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L22/32 ,  H01L22/14 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/09 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/06181 ,  H01L2224/06515 ,  H01L2224/09181 ,  H01L2224/16106 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/81801 ,  H01L2224/81908

Abstract: A semiconductor substrate including an upper surface and a lower surface may include a bump pad unit disposed on the upper surface. The semiconductor substrate may also include test pads disposed on the upper surface or the lower surface. The semiconductor substrate may also include traces configured to connect the bump pad unit and the test pads. The bump pad unit includes a main bump pad disposed on the upper surface, and a plurality of side bump pads disposed on the upper surface to be spaced apart from the main bump pad. The traces may connect the main bump pad and the plurality of side bump pads to the test pads in a one-to-one manner.

公开(公告)号：US20190206841A1

公开(公告)日：2019-07-04

申请号：US16106521

申请日：2018-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Lyong KIM ,  Seung Duk BAEK

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/5383 ,  H01L24/05 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05169 ,  H01L2224/05184 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/13007 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/013 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2924/01074 ,  H01L2924/01023 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/81

Abstract: A semiconductor package includes a first semiconductor chip having a first chip substrate, the first chip substrate having a first upper surface and a first lower surface opposite to each other, a first through-silicon via (TSV), a lower connection pad and a first lower passivation layer on the first lower surface of the first chip substrate, the first lower passivation layer exposing a portion of the lower connection pad, an upper connection pad and a first upper passivation layer on the first upper surface of the first chip substrate, the first upper passivation layer including a first upper inorganic material layer, and a second semiconductor chip connected to the first semiconductor chip, the second semiconductor chip including a second TSV, wherein the first lower passivation layer has a stacked structure of a first lower inorganic material layer and a lower organic material layer.

公开(公告)号：US20170186801A1

公开(公告)日：2017-06-29

申请号：US15461001

申请日：2017-03-16

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar

IPC: H01L27/146

CPC classification number: H01L27/14634 ,  H01L21/568 ,  H01L23/3114 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/46 ,  H01L24/48 ,  H01L24/49 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L27/14618 ,  H01L27/14636 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/09181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48101 ,  H01L2224/48227 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/143 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: In a microelectronic package, a first wire bond wire is coupled to an upper surface of a substrate. A first bond mass is coupled to another end of the first wire bond wire. A second wire bond wire is coupled to the upper surface. A second bond mass is coupled to another end of the second wire bond wire. The first and second wire bond wires laterally jut out horizontally away from the upper surface of the substrate for at least a distance of approximately 2 to 3 times a diameter of both the first wire bond wire and the second wire bond wire. The first wire bond wire and the second wire bond wire are horizontal for the distance with respect to being co-planar with the upper surface within +/−10 degrees.

公开(公告)号：US09601467B1

公开(公告)日：2017-03-21

申请号：US14845150

申请日：2015-09-03

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar

IPC: H01L23/48 ,  H01L23/52 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L27/14634 ,  H01L21/568 ,  H01L23/3114 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/46 ,  H01L24/48 ,  H01L24/49 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L27/14618 ,  H01L27/14636 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/09181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48101 ,  H01L2224/48227 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/143 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: In a microelectronic package, a first wire bond wire is coupled to an upper surface of a substrate. A first bond mass is coupled to another end of the first wire bond wire. A second wire bond wire is coupled to the upper surface. A second bond mass is coupled to another end of the second wire bond wire. The first and second wire bond wires laterally jut out horizontally away from the upper surface of the substrate for at least a distance of approximately 2 to 3 times a diameter of both the first wire bond wire and the second wire bond wire. The first wire bond wire and the second wire bond wire are horizontal for the distance with respect to being co-planar with the upper surface within +/−10 degrees.

公开(公告)号：US20170005027A1

公开(公告)日：2017-01-05

申请号：US15264245

申请日：2016-09-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Ming-Fa Chen ,  Wen-Ching Tsai

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/311 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/481 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/48 ,  H01L21/486 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/522 ,  H01L24/03 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/80 ,  H01L24/82 ,  H01L24/89 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02122 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/04105 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/24146 ,  H01L2224/80001 ,  H01L2224/80006 ,  H01L2224/80896 ,  H01L2224/82031 ,  H01L2224/821 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2224/80 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/82 ,  H01L2924/00014

Abstract: Disclosed herein is a package having a first redistribution layer (RDL) disposed on a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate. The first RDL is bonded to the second RDL. The package further includes an insulating film disposed over the second RDL and around the first RDL and the first semiconductor substrate. A conductive element is disposed in the first RDL. A via extends from a top surface of the insulating film, through the first semiconductor substrate to the conductive element, and a spacer is disposed between the first semiconductor substrate and the via. The spacer extends through the first semiconductor substrate.

Abstract translation: 本文公开了具有设置在第一半导体衬底上的第一再分布层（RDL）和设置在第二半导体衬底上的第二RDL的封装。 第一个RDL被绑定到第二个RDL。 封装还包括布置在第二RDL上并围绕第一RDL和第一半导体衬底的绝缘膜。 导电元件设置在第一RDL中。 通孔从绝缘膜的顶表面延伸穿过第一半导体衬底到导电元件，并且间隔物设置在第一半导体衬底和通孔之间。 间隔物延伸穿过第一半导体衬底。

公开(公告)号：US20160197060A1

公开(公告)日：2016-07-07

申请号：US15071920

申请日：2016-03-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Chang Yu ,  Kai-Chun Lin ,  Yue-Der Chih

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/065 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/06181 ,  H01L2224/09181 ,  H01L2224/131 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1712 ,  H01L2224/17179 ,  H01L2224/17181 ,  H01L2224/75702 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/9202 ,  H01L2225/06517 ,  H01L2225/06582 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/014

Abstract: A embodiment package includes a three dimensional integrated circuit (3D IC) with first input/output pads on a first side and second input/output pads on a second side, a first fan out structure electrically coupled to the first input/output pads on the first side of the three dimensional integrated circuit, and a second fan out structure electrically coupled to the second input/output pads on the second side of the three dimensional integrated circuit.

公开(公告)号：US09299677B2

公开(公告)日：2016-03-29

申请号：US14144813

申请日：2013-12-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Chang Yu ,  Kai-Chun Lin ,  Yue-Der Chih

IPC: H01L29/80 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/065 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/06181 ,  H01L2224/09181 ,  H01L2224/131 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1712 ,  H01L2224/17179 ,  H01L2224/17181 ,  H01L2224/75702 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/9202 ,  H01L2225/06517 ,  H01L2225/06582 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/014

Abstract: A embodiment package includes a three dimensional integrated circuit (3D IC) with first input/output pads on a first side and second input/output pads on a second side, a first fan out structure electrically coupled to the first input/output pads on the first side of the three dimensional integrated circuit, and a second fan out structure electrically coupled to the second input/output pads on the second side of the three dimensional integrated circuit.

Abstract translation: 实施例包装包括三维集成电路（3D IC），其具有第一侧上的第一输入/输出焊盘和第二侧上的第二输入/输出焊盘，电耦合到第二侧上的第一输入/输出焊盘的第一扇出结构 三维集成电路的第一侧，以及电耦合到三维集成电路的第二侧上的第二输入/输出焊盘的第二扇出结构。

公开(公告)号：US20150325520A1

公开(公告)日：2015-11-12

申请号：US14444681

申请日：2014-07-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Ming-Fa Chen ,  Wen-Ching Tsai ,  Sung-Feng Yeh

IPC: H01L23/538 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L25/065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76898 ,  H01L23/48 ,  H01L23/481 ,  H01L23/5384 ,  H01L24/03 ,  H01L24/06 ,  H01L24/08 ,  H01L24/19 ,  H01L24/24 ,  H01L24/80 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/0212 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/11 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/18 ,  H01L2224/24146 ,  H01L2224/73267 ,  H01L2224/80896 ,  H01L2224/82031 ,  H01L2224/821 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2924/18162 ,  H01L2224/03 ,  H01L2224/80001 ,  H01L2924/00014 ,  H01L2224/82 ,  H01L2924/014

Abstract: Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.

Abstract translation: 本文公开了一种包括设置在第一半导体衬底的第一侧上的第一再分配层（RDL）和布置在第二半导体衬底上的第二RDL的封装，其中第一RDL被结合到第二RDL。 第一导电元件设置在第一RDL和第二RDL中。 第一通孔从一个或多个第一导电元件通过第一半导体衬底延伸到与第一侧相对的第一半导体衬底的第二侧。 第一间隔物介于第一半导体衬底和第一通孔之间，并且各自通过第一半导体衬底从相应的一个第一导电元件延伸。