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公开(公告)号：US20210288656A1
公开(公告)日：2021-09-16
申请号：US17200426
申请日：2021-03-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Raghu GANESAN , Saravanakkumar RADHAKRISHNAN , Kalpesh Laxmanbhai RAJAI , Soumyajit ROUL , Sumantra SETH
Abstract: A receiver circuit includes an interleaved ADC, a first delay circuit, a second delay circuit, a first processing channel, a second processing channel, and an interleaving ADC timing error detector circuit. The interleaved ADC includes a first ADC and a second ADC in parallel. The first delay circuit delays a first clock signal provided to the first ADC. The second delay circuit delays a second clock signal provided to the second ADC. The first processing channel processes data samples provided by the first ADC, and includes a first slicer. The second processing channel processes data samples provided by the second ADC, and includes a second slicer. The interleaving ADC timing error detector circuit controls delay of the first delay circuit and the second delay circuit based on an output signal of the first slicer, and an output signal or an input signal of the second slicer.
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公开(公告)号：US20210288836A1
公开(公告)日：2021-09-16
申请号：US17082208
申请日：2020-10-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Raghu GANESAN , Saravanakkumar Radhakrishana , Gaurav Aggarwal
Abstract: A receiver circuit includes a feedback loop including a device. The receiver circuit also includes a register and a sequencer. The sequencer is configured to, responsive to an error signal being below a threshold value, cause the register to store a value indicative of the state of the feedback loop. The sequencer is also configured to cause the feedback loop to transition to a lower power state, and, responsive to a detected wake-up event, cause the previously stored value indicative of the state of the feedback loop to be loaded from the register into the device and enable the feedback loop.
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Patent Agency Ranking
公开(公告)号：US20210288684A1
公开(公告)日：2021-09-16
申请号：US17200060
申请日：2021-03-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Raghu GANESAN , Gaurav AGGARWAL , Rahul KOPPISETTI , Rallabandi V Lakshmi ANNAPURNA , Saravanakkumar RADHAKRISHNAN , Kalpesh Laxmanbhai RAJAI
Abstract: A receiver circuit includes an ADC, a processing channel, and an interference detection path. The processing channel is configured to process data samples provided by the ADC, and includes a notch filter. The interference detection path is configured to detect interference in the data samples, and includes a slicer, a slicer error circuit, and an interference detection circuit. The slicer is configured to slice input of the notch filter. The slicer error circuit is configured to compute an error of the slicer. The interference detection circuit configured to detect an interference signal in the error of the slicer, and set the notch filter to attenuate the interference signal.
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公开(公告)号：US20210288826A1
公开(公告)日：2021-09-16
申请号：US17199142
申请日：2021-03-11
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Kalpesh Laxmanbhai RAJAI , Saravanakkumar RADHAKRISHNAN , Gaurav AGGARWAL , Raghu GANESAN , Rallabandi V. Lakshmi ANNAPURNA
Abstract: A method includes receiving an input signal at a filter, where the filter includes a plurality of filter taps, and where each of a first filter tap and a second filter tap has a weighting coefficient. The method also includes shutting down the first filter tap based on the weighting coefficient of the first filter tap being below a threshold and the weighting coefficient of the second filter tap being below the threshold, where the second filter tap is next to the first filter tap.
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公开(公告)号：US20210014087A1
公开(公告)日：2021-01-14
申请号：US17037140
申请日：2020-09-29
Applicant: Texas Instruments Incorporated
Abstract: A device includes a receiver having analog front-end circuitry and a digital signal processing (DSP) circuit. The DSP circuit is configured to select one of a plurality of digital equalization (DEQ) filter options and to perform DEQ operations based on the selected DEQ filter option, wherein the DSP circuit is configured to select one of the plurality of DEQ filter options based on a channel length estimate and a plurality of different sets of DEQ filter coefficients predetermined for different channel lengths.
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公开(公告)号：US20200092144A1
公开(公告)日：2020-03-19
申请号：US16575151
申请日：2019-09-18
Applicant: Texas Instruments Incorporated
Abstract: A device includes a receiver having analog front-end circuitry and a digital signal processing (DSP) circuit. The DSP circuit is configured to select one of a plurality of digital equalization (DEQ) filter options and to perform DEQ operations based on the selected DEQ filter option, wherein the DSP circuit is configured to select one of the plurality of DEQ filter options based on a channel length estimate and a plurality of different sets of DEQ filter coefficients predetermined for different channel lengths.
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公开(公告)号：US20170302310A1
公开(公告)日：2017-10-19
申请号：US15486909
申请日：2017-04-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Subhashish MUKHERJEE , Yogesh DARWHEKAR , Nagaraj V. DIXIT , Raghu GANESAN
IPC: H04B1/10 , H04B17/318 , H04B17/345 , H04B1/16 , H03L7/099 , H03G3/20
CPC classification number: H04B1/10 , H03G3/3052 , H03J7/00 , H03L7/087 , H03L7/099 , H03L7/18 , H04B1/123 , H04B1/16 , H04B17/318
Abstract: At least some embodiments are directed to a receiver system that comprises a first oscillation module configured to provide oscillating signals of differing frequencies and a second oscillation module configured to provide other oscillating signals of the differing frequencies. The second oscillation module is configured to produce less noise than the first oscillation module. A controller is coupled to the first and second oscillation modules and configured to selectively activate and deactivate each of the first and second oscillation modules based on signal strengths of primary signals received via a wireless medium and based on signal strengths of interference signals received via the wireless medium.
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