公开(公告)号：US20210288656A1

公开(公告)日：2021-09-16

申请号：US17200426

申请日：2021-03-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raghu GANESAN ,  Saravanakkumar RADHAKRISHNAN ,  Kalpesh Laxmanbhai RAJAI ,  Soumyajit ROUL ,  Sumantra SETH

IPC: H03M1/06 ,  H03M1/50 ,  H03M1/00

Abstract: A receiver circuit includes an interleaved ADC, a first delay circuit, a second delay circuit, a first processing channel, a second processing channel, and an interleaving ADC timing error detector circuit. The interleaved ADC includes a first ADC and a second ADC in parallel. The first delay circuit delays a first clock signal provided to the first ADC. The second delay circuit delays a second clock signal provided to the second ADC. The first processing channel processes data samples provided by the first ADC, and includes a first slicer. The second processing channel processes data samples provided by the second ADC, and includes a second slicer. The interleaving ADC timing error detector circuit controls delay of the first delay circuit and the second delay circuit based on an output signal of the first slicer, and an output signal or an input signal of the second slicer.