公开(公告)号：US20210288826A1

公开(公告)日：2021-09-16

申请号：US17199142

申请日：2021-03-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kalpesh Laxmanbhai RAJAI ,  Saravanakkumar RADHAKRISHNAN ,  Gaurav AGGARWAL ,  Raghu GANESAN ,  Rallabandi V. Lakshmi ANNAPURNA

IPC: H04L12/12 ,  H04L25/03 ,  H03H17/06

Abstract: A method includes receiving an input signal at a filter, where the filter includes a plurality of filter taps, and where each of a first filter tap and a second filter tap has a weighting coefficient. The method also includes shutting down the first filter tap based on the weighting coefficient of the first filter tap being below a threshold and the weighting coefficient of the second filter tap being below the threshold, where the second filter tap is next to the first filter tap.

公开(公告)号：US20210288684A1

公开(公告)日：2021-09-16

申请号：US17200060

申请日：2021-03-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raghu GANESAN ,  Gaurav AGGARWAL ,  Rahul KOPPISETTI ,  Rallabandi V Lakshmi ANNAPURNA ,  Saravanakkumar RADHAKRISHNAN ,  Kalpesh Laxmanbhai RAJAI

IPC: H04B1/10 ,  H04B1/16 ,  H04B1/12

Abstract: A receiver circuit includes an ADC, a processing channel, and an interference detection path. The processing channel is configured to process data samples provided by the ADC, and includes a notch filter. The interference detection path is configured to detect interference in the data samples, and includes a slicer, a slicer error circuit, and an interference detection circuit. The slicer is configured to slice input of the notch filter. The slicer error circuit is configured to compute an error of the slicer. The interference detection circuit configured to detect an interference signal in the error of the slicer, and set the notch filter to attenuate the interference signal.

公开(公告)号：US20210288656A1

公开(公告)日：2021-09-16

申请号：US17200426

申请日：2021-03-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raghu GANESAN ,  Saravanakkumar RADHAKRISHNAN ,  Kalpesh Laxmanbhai RAJAI ,  Soumyajit ROUL ,  Sumantra SETH

IPC: H03M1/06 ,  H03M1/50 ,  H03M1/00

Abstract: A receiver circuit includes an interleaved ADC, a first delay circuit, a second delay circuit, a first processing channel, a second processing channel, and an interleaving ADC timing error detector circuit. The interleaved ADC includes a first ADC and a second ADC in parallel. The first delay circuit delays a first clock signal provided to the first ADC. The second delay circuit delays a second clock signal provided to the second ADC. The first processing channel processes data samples provided by the first ADC, and includes a first slicer. The second processing channel processes data samples provided by the second ADC, and includes a second slicer. The interleaving ADC timing error detector circuit controls delay of the first delay circuit and the second delay circuit based on an output signal of the first slicer, and an output signal or an input signal of the second slicer.