公开(公告)号：US20210194429A1

公开(公告)日：2021-06-24

申请号：US17074688

申请日：2020-10-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sumantra SETH ,  Isha KHANDELWAL ,  Rama Santosh Neelim Kumar KATTAMURI

IPC: H03B5/36 ,  H03H7/06

Abstract: An integrated circuit includes an inverter, first and second capacitors, a resistor, and a transistor. The inverter has an input and an output. The first capacitor is coupled to a ground. The transistor has a first transistor terminal, a second transistor terminal, and a control input. The first transistor terminal is coupled to the first capacitor and the second transistor terminal is coupled to the input of the inverter. The second capacitor is coupled between the output of the inverter and the ground. The resistor is coupled between the output of the inverter and the first transistor terminal.

公开(公告)号：US20190179398A1

公开(公告)日：2019-06-13

申请号：US15838593

申请日：2017-12-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anurag ARORA ,  Vikram SHARMA ,  Sumantra SETH

IPC: G06F1/32

Abstract: A wakeup circuit includes an energy detection circuit and a wakeup signal generation circuit coupled to the energy detection circuit. The energy detection circuit is configured to, in response to receiving an input signal, generate a detect signal that is proportional to the input signal. The energy detection circuit is powered by the input signal. The wakeup signal generation circuit is configured to, in response to receiving the detect signal, generate a wakeup signal.

公开(公告)号：US20220029585A1

公开(公告)日：2022-01-27

申请号：US17495097

申请日：2021-10-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sumantra SETH ,  Isha KHANDELWAL ,  Rama Santosh Neelim Kumar KATTAMURI

IPC: H03B5/36 ,  H03H7/06

Abstract: An integrated circuit includes an inverter, first and second capacitors, a resistor, and a transistor. The inverter has an input and an output. The first capacitor is coupled to a ground. The transistor has a first transistor terminal, a second transistor terminal, and a control input. The first transistor terminal is coupled to the first capacitor and the second transistor terminal is coupled to the input of the inverter. The second capacitor is coupled between the output of the inverter and the ground. The resistor is coupled between the output of the inverter and the first transistor terminal.

公开(公告)号：US20210288656A1

公开(公告)日：2021-09-16

申请号：US17200426

申请日：2021-03-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raghu GANESAN ,  Saravanakkumar RADHAKRISHNAN ,  Kalpesh Laxmanbhai RAJAI ,  Soumyajit ROUL ,  Sumantra SETH

IPC: H03M1/06 ,  H03M1/50 ,  H03M1/00

Abstract: A receiver circuit includes an interleaved ADC, a first delay circuit, a second delay circuit, a first processing channel, a second processing channel, and an interleaving ADC timing error detector circuit. The interleaved ADC includes a first ADC and a second ADC in parallel. The first delay circuit delays a first clock signal provided to the first ADC. The second delay circuit delays a second clock signal provided to the second ADC. The first processing channel processes data samples provided by the first ADC, and includes a first slicer. The second processing channel processes data samples provided by the second ADC, and includes a second slicer. The interleaving ADC timing error detector circuit controls delay of the first delay circuit and the second delay circuit based on an output signal of the first slicer, and an output signal or an input signal of the second slicer.

公开(公告)号：US20200267028A1

公开(公告)日：2020-08-20

申请号：US16701717

申请日：2019-12-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rama Santosh Neelim Kumar KATTAMURI ,  Sumantra SETH ,  Vikram SHARMA

IPC: H04L25/02 ,  H04L25/49 ,  H03F3/45 ,  H03F3/21

Abstract: A line driver circuit includes a first input terminal, a second input terminal, a first input stage, a second input stage, a first output stage, and a second output stage. The first input stage includes a first input coupled to the first input terminal, and a second input coupled to the second input terminal. The second input stage includes a first input coupled to the first input terminal, and a second input coupled to the second input terminal. The first output stage includes a first input coupled to a first output terminal of the first input stage and a second input coupled to a first output terminal of the first input stage. A second output stage includes a first input coupled to a second output terminal of the first input stage and a second input coupled to a second output terminal of the first input stage.

公开(公告)号：US20180309447A1

公开(公告)日：2018-10-25

申请号：US15849752

申请日：2017-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anurag ARORA ,  Hariharan NAGARAJAN ,  Sumantra SETH

IPC: H03K19/00 ,  H04L12/12

CPC classification number: H03K19/0016 ,  H04L12/12 ,  H04L12/40006

Abstract: A wakeup circuit includes an amplification stage circuit and a filter stage circuit. The amplification stage circuit is configured to, in response to receiving an input signal, generate an amplified digital signal that is proportional to the input signal. The filter stage circuit is configured to, in response to receiving a threshold number of toggles of the amplified digital signal within a pre-defined time period (such as one clock period of a clock signal), generate a wakeup signal as an output signal of the filter stage circuit.