公开(公告)号：US20150187597A1

公开(公告)日：2015-07-02

申请号：US14576617

申请日：2014-12-19

Applicant: Texas Instruments Incorporated

Inventor： Bradley David SUCHER ,  Rick L. WISE

IPC: H01L21/324 ,  H01L21/02

CPC classification number: H01L21/3225

Abstract: By controlling the concentration and size of bulk micro defects (BMD) during the manufacture of an integrated circuit slip and associated yield loss due to slip may be eliminated. A process for eliminating slip that is customized to an integrated circuit (IC) manufacturing flow is disclosed. The process is adapted to the oxygen content of the starting material and to the thermal budget of an IC manufacturing flow and generates a sufficient concentration of BMDs of a size that is optimized to getter microcracks thereby eliminating slip. Slip is eliminated in unpatterned wafers and in wafers containing shallow trench isolation and deep trench isolation using a BMD nucleation anneal and a BMD growth anneal.

Abstract translation: 通过控制在集成电路滑移的制造过程中的体积微缺陷（BMD）的浓度和尺寸以及由于滑动引起的相关的成品率损失可以被消除。 公开了一种消除针对集成电路（IC）制造流程定制的滑移的过程。 该方法适用于起始材料的氧含量和IC制造流程的热预算，并且产生足够浓度的BMD，其尺寸被优化以消除微裂纹从而消除滑移。 在未图案化的晶片和含有浅沟槽隔离的晶片和使用BMD成核退火和BMD生长退火的深沟槽隔离的晶片中消除了滑移。

公开(公告)号：US20140339678A1

公开(公告)日：2014-11-20

申请号：US14450857

申请日：2014-08-04

Applicant: Texas Instruments Incorporated

Inventor： Rick L. WISE ,  Hiroshi YASUDA

IPC: H01L29/36 ,  H01L29/73

CPC classification number: H01L29/36 ,  H01L21/02063 ,  H01L21/2254 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/73 ,  H01L29/7325

Abstract: An integrated circuit containing a bipolar transistor including an emitter diffused region with a peak doping density higher than 1·1020 atoms/cm3, and an emitter-base junction less than 40 nanometers deep in a base layer. A process of forming the bipolar transistor, which includes forming an emitter dopant atom layer between a base layer and an emitter layer, followed by a flash or laser anneal step to diffuse dopant atoms from the emitter dopant atom layer into the base layer.

Abstract translation: 一种包含双极晶体管的集成电路，其包括具有高于1×1020原子/ cm3的峰值掺杂密度的发射极扩散区域，以及在基极层中小于40纳米深的发射极 - 基极结。 一种形成双极晶体管的工艺，其包括在基极层和发射极层之间形成发射极掺杂剂原子层，随后进行闪光或激光退火步骤，以将掺杂剂原子从发射极掺杂剂原子层扩散到基底层中。

公开(公告)号：US20140329370A1

公开(公告)日：2014-11-06

申请号：US13886652

申请日：2013-05-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen TIPIRNENI ,  Sameer PENDHARKAR ,  Rick L. WISE

IPC: H01L21/02

CPC classification number: H01L21/187 ,  H01L21/76254 ,  H01L21/8258

Abstract: An integrated silicon and III-N semiconductor device may be formed by growing III-N semiconductor material on a first silicon substrate having a first orientation. A second silicon substrate with a second, different, orientation has a release layer between a silicon device film and a carrier wafer. The silicon device film is attached to the III-N semiconductor material while the silicon device film is connected to the carrier wafer through the release layer. The carrier wafer is subsequently removed from the silicon device film. A first plurality of components is formed in and/or on the silicon device film. A second plurality of components is formed in and/or on III-N semiconductor material in the exposed region. In an alternate process, a dielectric interlayer may be disposed between the silicon device film and the III-N semiconductor material in the integrated silicon and III-N semiconductor device.

Abstract translation: 可以通过在具有第一取向的第一硅衬底上生长III-N半导体材料来形成集成的硅和III-N半导体器件。 具有第二不同取向的第二硅衬底在硅器件膜和载体晶片之间具有释放层。 硅器件膜附着到III-N半导体材料上，而硅器件膜通过释放层连接到载体晶片。 随后从硅器件膜移除载体晶片。 在硅器件膜上和/或上形成第一多个部件。 在暴露区域中的III-N半导体材料中和/或上形成第二组分。 在替代方法中，可以在集成硅和III-N半导体器件中的硅器件膜和III-N半导体材料之间设置电介质中间层。