公开(公告)号：US20240274530A1

公开(公告)日：2024-08-15

申请号：US18107600

申请日：2023-02-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Siraj Akhtar ,  Vineethraj Rajappan Nair ,  Robert Taft ,  Swaminathan Sankaran

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/08113 ,  H01L2224/16054 ,  H01L2224/16055 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/48225 ,  H01L2224/48465 ,  H01L2924/15311

Abstract: An integrated circuit includes a semiconductor die, a package substrate having opposite first and second surfaces, where the first surface includes a first metal pad, the second surface includes a second metal pad and a third metal pad. The semiconductor die is mounted on the second metal pad and the third metal pad by respective first and second metal interconnects. The package substrate includes a circuit with a single-ended terminal and a pair of differential terminals, where the single-ended terminal coupled to the first metal pad. The backage substrate also includes a metal layer including a first meandered conductor and a second meandered conductor. The first meandered conductor is coupled between a first terminal of the pair of differential terminals and the second metal pad. The second meandered conductor is coupled between a second terminal of the pair of differential terminals and the third metal pad.

公开(公告)号：US20250080117A1

公开(公告)日：2025-03-06

申请号：US18240278

申请日：2023-08-30

Applicant: Texas Instruments Incorporated

Inventor： Robert Taft ,  Alexander Bodem ,  Filip Savic ,  Paul Kramer ,  Vineethraj Rajappan Nair

IPC: H03K21/00 ,  H03K19/20

Abstract: An example apparatus includes: first through eighth gated inverters each having inputs and outputs; a first and second inverter each having an input and an output, the output of the first inverter coupled to the input of the second gated inverter, the output of the second inverter coupled to the input of the third gated inverter; the fifth gated inverter coupled to the input of the first gated inverter and the input of the first inverter; the sixth gated inverter coupled to the input of the second inverter and the input of the fourth gated inverter; the seventh gated inverter coupled to the output of the first gated inverter and the output of the third gated inverter; the eighth gated inverter coupled to the output of the second gated inverter and the output of the fourth gated inverter; and a bus-holder circuit between the seventh and eighth gated inverter inputs.