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公开(公告)号：US20180337665A1
公开(公告)日：2018-11-22
申请号：US15974956
申请日：2018-05-09
Applicant: Texas Instruments Incorporated
Inventor： Robert Callaghan Taft , Vineethraj Rajappan Nair
IPC: H03K5/14
CPC classification number: H03K5/14 , H03K2005/00019
Abstract: In described examples, an electronic circuit for delaying a signal (received at an input node) includes a delay line with multiple tap locations, a tap line proximate to the delay line and coupled to an output node, and multiple groups of switches. Switches in the groups of switches are severally coupled between tap locations corresponding to the respective group of switches, and the tap line. When the signal is propagated through the delay line, a first number of the switches corresponding to a selected tap location are closed, a second number of the switches corresponding to an adjacent tap location are closed, and the signal is transmitted with a delay through the closed switches, to the tap line, to the output node. The delay includes an average, weighted using the first and second numbers, of delays corresponding to the selected and adjacent tap locations.
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公开(公告)号：US20250080117A1
公开(公告)日：2025-03-06
申请号：US18240278
申请日：2023-08-30
Applicant: Texas Instruments Incorporated
Inventor： Robert Taft , Alexander Bodem , Filip Savic , Paul Kramer , Vineethraj Rajappan Nair
Abstract: An example apparatus includes: first through eighth gated inverters each having inputs and outputs; a first and second inverter each having an input and an output, the output of the first inverter coupled to the input of the second gated inverter, the output of the second inverter coupled to the input of the third gated inverter; the fifth gated inverter coupled to the input of the first gated inverter and the input of the first inverter; the sixth gated inverter coupled to the input of the second inverter and the input of the fourth gated inverter; the seventh gated inverter coupled to the output of the first gated inverter and the output of the third gated inverter; the eighth gated inverter coupled to the output of the second gated inverter and the output of the fourth gated inverter; and a bus-holder circuit between the seventh and eighth gated inverter inputs.
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公开(公告)号：US20210356984A1
公开(公告)日：2021-11-18
申请号：US17386591
申请日：2021-07-28
Applicant: Texas Instruments Incorporated
Inventor： Robert Callaghan Taft , Vineethraj Rajappan Nair
Abstract: An electronic circuit which is a high speed CMOS logic circuit to divide the frequency of an input signal is provided. The electronic circuit comprises a ring oscillator. The ring oscillator comprises a plurality of gated inverters. At least one of the gated inverters is configured to receive an oscillating signal and a control signal at two complementary inputs. The electronic circuit is configured to be partially gated such that a divide ratio is selectable. By means of clock partial gating, open loop clock buffering and avoiding slow combinatory logic in the data path, a very high speed multi-moduli clock divider is achieved.
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Patent Agency Ranking
公开(公告)号：US20240274530A1
公开(公告)日：2024-08-15
申请号：US18107600
申请日：2023-02-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Siraj Akhtar , Vineethraj Rajappan Nair , Robert Taft , Swaminathan Sankaran
IPC: H01L23/528 , H01L23/00 , H01L23/522
CPC classification number: H01L23/528 , H01L23/5226 , H01L24/08 , H01L24/16 , H01L24/48 , H01L2224/08113 , H01L2224/16054 , H01L2224/16055 , H01L2224/16235 , H01L2224/16238 , H01L2224/48225 , H01L2224/48465 , H01L2924/15311
Abstract: An integrated circuit includes a semiconductor die, a package substrate having opposite first and second surfaces, where the first surface includes a first metal pad, the second surface includes a second metal pad and a third metal pad. The semiconductor die is mounted on the second metal pad and the third metal pad by respective first and second metal interconnects. The package substrate includes a circuit with a single-ended terminal and a pair of differential terminals, where the single-ended terminal coupled to the first metal pad. The backage substrate also includes a metal layer including a first meandered conductor and a second meandered conductor. The first meandered conductor is coupled between a first terminal of the pair of differential terminals and the second metal pad. The second meandered conductor is coupled between a second terminal of the pair of differential terminals and the third metal pad.
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公开(公告)号：US20210026397A1
公开(公告)日：2021-01-28
申请号：US16935240
申请日：2020-07-22
Applicant: Texas Instruments Incorporated
Inventor： Robert Callaghan Taft , Vineethraj Rajappan Nair
Abstract: An electronic circuit which is a high speed CMOS logic circuit to divide the frequency of an input signal is provided. The electronic circuit comprises a ring oscillator. The ring oscillator comprises a plurality of gated inverters. At least one of the gated inverters is configured to receive an oscillating signal and a control signal at two complementary inputs. The electronic circuit is configured to be partially gated such that a divide ratio is selectable. By means of clock partial gating, open loop clock buffering and avoiding slow combinatory logic in the data path, a very high speed multi-moduli clock divider is achieved.
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公开(公告)号：US11429136B2
公开(公告)日：2022-08-30
申请号：US17386591
申请日：2021-07-28
Applicant: Texas Instruments Incorporated
Inventor： Robert Callaghan Taft , Vineethraj Rajappan Nair
Abstract: An electronic circuit which is a high speed CMOS logic circuit to divide the frequency of an input signal is provided. The electronic circuit comprises a ring oscillator. The ring oscillator comprises a plurality of gated inverters. At least one of the gated inverters is configured to receive an oscillating signal and a control signal at two complementary inputs. The electronic circuit is configured to be partially gated such that a divide ratio is selectable. By means of clock partial gating, open loop clock buffering and avoiding slow combinatory logic in the data path, a very high speed multi-moduli clock divider is achieved.
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公开(公告)号：US11106236B2
公开(公告)日：2021-08-31
申请号：US16935240
申请日：2020-07-22
Applicant: Texas Instruments Incorporated
Inventor： Robert Callaghan Taft , Vineethraj Rajappan Nair
Abstract: An electronic circuit which is a high speed CMOS logic circuit to divide the frequency of an input signal is provided. The electronic circuit comprises a ring oscillator. The ring oscillator comprises a plurality of gated inverters. At least one of the gated inverters is configured to receive an oscillating signal and a control signal at two complementary inputs. The electronic circuit is configured to be partially gated such that a divide ratio is selectable. By means of clock partial gating, open loop clock buffering and avoiding slow combinatory logic in the data path, a very high speed multi-moduli clock divider is achieved.
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公开(公告)号：US10547295B2
公开(公告)日：2020-01-28
申请号：US15974956
申请日：2018-05-09
Applicant: Texas Instruments Incorporated
Inventor： Robert Callaghan Taft , Vineethraj Rajappan Nair
Abstract: In described examples, an electronic circuit for delaying a signal (received at an input node) includes a delay line with multiple tap locations, a tap line proximate to the delay line and coupled to an output node, and multiple groups of switches. Switches in the groups of switches are severally coupled between tap locations corresponding to the respective group of switches, and the tap line. When the signal is propagated through the delay line, a first number of the switches corresponding to a selected tap location are closed, a second number of the switches corresponding to an adjacent tap location are closed, and the signal is transmitted with a delay through the closed switches, to the tap line, to the output node. The delay includes an average, weighted using the first and second numbers, of delays corresponding to the selected and adjacent tap locations.
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