公开(公告)号：US20240363394A1

公开(公告)日：2024-10-31

申请号：US18141153

申请日：2023-04-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Sunglyong Kim ,  Meng-Chia Lee ,  Satoshi Suzuki ,  Seetharaman Sridhar

IPC: H01L21/761 ,  H01L27/088

CPC classification number: H01L21/761 ,  H01L27/088 ,  H01L21/2652 ,  H01L21/266 ,  H01L29/66681

Abstract: Described examples include an integrated circuit having a substrate, a first doped region in the substrate having a first conductivity type, and a first epitaxial layer on the substrate, wherein the first doped region extends into the first epitaxial layer. The integrated circuit also has a second doped region in the first epitaxial layer having the first conductivity type, a second epitaxial layer on the first epitaxial layer, wherein the second doped region extends into the second epitaxial layer. The integrated circuit also has a well in the second epitaxial layer having a second conductivity type, and a first active device formed in the well.

公开(公告)号：US20160240667A1

公开(公告)日：2016-08-18

申请号：US15138955

申请日：2016-04-26

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon ,  Hideaki Kawahara ,  Simon John Malloy ,  Satoshi Suzuki ,  John Manning Savidge Neilson

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of the MOSFET. A split gate with a central opening is disposed above the drain drift region between the RESURF trenches. A two-level LDD region is disposed below the central opening in the split gate. A contact metal stack makes contact with a source region at lateral sides of the triple contact structure, and with a body contact region and the field plates in the RESURF trenches at a bottom surface of the triple contact structure. A perimeter RESURF trench surrounds the MOSFET. A field plate in the perimeter RESURF trench is electrically coupled to the source electrode of the MOSFET. An integrated snubber may be formed in trenches formed concurrently with the RESURF trenches.

Abstract translation: 半导体器件包括中等电压MOSFET，其在包含场耦合到MOSFET的源电极的场板的RESURF沟槽之间具有垂直漏极漂移区。 具有中心开口的分流栅设置在RESURF沟槽之间的漏极漂移区的上方。 两级LDD区域设置在分裂门的中心开口下方。 接触金属叠层与三接触结构的侧面处的源极区域接触，并且在三触点结构的底表面处与主体接触区域和RESURF沟槽中的场板接触。 周边RESURF沟槽围绕着MOSFET。 外围RESURF沟槽中的场板电耦合到MOSFET的源电极。 集成缓冲器可以形成在与RESURF沟槽同时形成的沟槽中。

公开(公告)号：US10811533B2

公开(公告)日：2020-10-20

申请号：US15139496

申请日：2016-04-27

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon ,  Hideaki Kawahara ,  Simon John Molloy ,  Satoshi Suzuki ,  John Manning Savidge Neilson

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/786 ,  H01L21/311 ,  H01L29/10 ,  H01L29/417 ,  H01L29/45

Abstract: A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of the MOSFET. A split gate with a central opening is disposed above the drain drift region between the RESURF trenches. A two-level LDD region is disposed below the central opening in the split gate. A contact metal stack makes contact with a source region at lateral sides of the triple contact structure, and with a body contact region and the field plates in the RESURF trenches at a bottom surface of the triple contact structure. A perimeter RESURF trench surrounds the MOSFET. A field plate in the perimeter RESURF trench is electrically coupled to the source electrode of the MOSFET. An integrated snubber may be formed in trenches formed concurrently with the RESURF trenches.

公开(公告)号：US10553717B2

公开(公告)日：2020-02-04

申请号：US15138955

申请日：2016-04-26

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon ,  Hideaki Kawahara ,  Simon John Molloy ,  Satoshi Suzuki ,  John Manning Savidge Neilson

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L21/311 ,  H01L29/10 ,  H01L29/417 ,  H01L29/45 ,  H01L29/786

Abstract: A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of the MOSFET. A split gate with a central opening is disposed above the drain drift region between the RESURF trenches. A two-level LDD region is disposed below the central opening in the split gate. A contact metal stack makes contact with a source region at lateral sides of the triple contact structure, and with a body contact region and the field plates in the RESURF trenches at a bottom surface of the triple contact structure. A perimeter RESURF trench surrounds the MOSFET. A field plate in the perimeter RESURF trench is electrically coupled to the source electrode of the MOSFET. An integrated snubber may be formed in trenches formed concurrently with the RESURF trenches.

公开(公告)号：US20190259868A1

公开(公告)日：2019-08-22

申请号：US16277719

申请日：2019-02-15

Applicant: Texas Instruments Incorporated

Inventor： Hideaki Kawahara ,  Christopher Boguslaw Kocon ,  Seetharaman Sridhar ,  Satoshi Suzuki ,  Simon John Molloy

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/417 ,  H01L29/40

Abstract: A device includes a transistor formed on a substrate. The transistor includes an n-type drain contact layer, an n-type drain layer, an oxide layer, a p-type body region, a p-type terminal region, body trenches, and terminal trenches. The n-type drain contact layer is near a bottom surface of the substrate. The n-type drain layer is positioned on the n-type drain contact layer. The oxide layer circumscribes a transistor region. The p-type body region is positioned within the transistor region. The p-type terminal region extends from under the oxide layer to an edge of the transistor region, thereby forming a contiguous junction with the p-type body region. The body trenches is within the transistor region and interleaves with the p-type body region, whereas the terminal trenches is outside the transistor region and interleaves with the p-type terminal region.

公开(公告)号：US10256337B2

公开(公告)日：2019-04-09

申请号：US15427489

申请日：2017-02-08

Applicant: Texas Instruments Incorporated

Inventor： Hideaki Kawahara ,  Christopher Boguslaw Kocon ,  Seetharaman Sridhar ,  Simon John Molloy ,  Satoshi Suzuki

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40

Abstract: A device includes a transistor formed on a substrate. The transistor includes an n-type drain contact layer, an n-type drain layer, an oxide layer, a p-type body region, a p-type terminal region, body trenches, and terminal trenches. The n-type drain contact layer is near a bottom surface of the substrate. The n-type drain layer is positioned on the n-type drain contact layer. The oxide layer circumscribes a transistor region. The p-type body region is positioned within the transistor region. The p-type terminal region extends from under the oxide layer to an edge of the transistor region, thereby forming a contiguous junction with the p-type body region. The body trenches is within the transistor region and interleaves with the p-type body region, whereas the terminal trenches is outside the transistor region and interleaves with the p-type terminal region.

公开(公告)号：US20160240653A1

公开(公告)日：2016-08-18

申请号：US15139496

申请日：2016-04-27

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon ,  Hideaki Kawahara ,  Simon John Molloy ,  Satoshi Suzuki ,  John Manning Savidge Neilson

IPC: H01L29/78 ,  H01L21/311 ,  H01L29/417 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of the MOSFET. A split gate with a central opening is disposed above the drain drift region between the RESURF trenches. A two-level LDD region is disposed below the central opening in the split gate. A contact metal stack makes contact with a source region at lateral sides of the triple contact structure, and with a body contact region and the field plates in the RESURF trenches at a bottom surface of the triple contact structure. A perimeter RESURF trench surrounds the MOSFET. A field plate in the perimeter RESURF trench is electrically coupled to the source electrode of the MOSFET. An integrated snubber may be formed in trenches formed concurrently with the RESURF trenches.

公开(公告)号：US10672901B2

公开(公告)日：2020-06-02

申请号：US16277719

申请日：2019-02-15

Applicant: Texas Instruments Incorporated

Inventor： Hideaki Kawahara ,  Christopher Boguslaw Kocon ,  Seetharaman Sridhar ,  Satoshi Suzuki ,  Simon John Molloy

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

Abstract: A device includes a transistor formed on a substrate. The transistor includes an n-type drain contact layer, an n-type drain layer, an oxide layer, a p-type body region, a p-type terminal region, body trenches, and terminal trenches. The n-type drain contact layer is near a bottom surface of the substrate. The n-type drain layer is positioned on the n-type drain contact layer. The oxide layer circumscribes a transistor region. The p-type body region is positioned within the transistor region. The p-type terminal region extends from under the oxide layer to an edge of the transistor region, thereby forming a contiguous junction with the p-type body region. The body trenches is within the transistor region and interleaves with the p-type body region, whereas the terminal trenches is outside the transistor region and interleaves with the p-type terminal region.

公开(公告)号：US20180226502A1

公开(公告)日：2018-08-09

申请号：US15427489

申请日：2017-02-08

Applicant: Texas Instruments Incorporated

Inventor： Hideaki Kawahara ,  Christopher Boguslaw Kocon ,  Seetharaman Sridhar ,  Simon John Molloy ,  Satoshi Suzuki

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L29/7802 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/7811

Abstract: A device includes a transistor formed on a substrate. The transistor includes an n-type drain contact layer, an n-type drain layer, an oxide layer, a p-type body region, a p-type terminal region, body trenches, and terminal trenches. The n-type drain contact layer is near a bottom surface of the substrate. The n-type drain layer is positioned on the n-type drain contact layer. The oxide layer circumscribes a transistor region. The p-type body region is positioned within the transistor region. The p-type terminal region extends from under the oxide layer to an edge of the transistor region, thereby forming a contiguous junction with the p-type body region. The body trenches is within the transistor region and interleaves with the p-type body region, whereas the terminal trenches is outside the transistor region and interleaves with the p-type terminal region.

公开(公告)号：US09905638B1

公开(公告)日：2018-02-27

申请号：US15281865

申请日：2016-09-30

Applicant: Texas Instruments Incorporated

Inventor： Tatsuya Tominari ,  Satoshi Suzuki ,  Seetharaman Sridhar ,  Christopher Boguslaw Kocon ,  Simon John Molloy ,  Hideaki Kawahara

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L29/167

CPC classification number: H01L29/0634 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/167

Abstract: A method of forming a semiconductor device includes etching a high aspect ratio, substantially perpendicular trench in a semiconductor region doped with a first dopant having first conductivity type and performing a first cycle for depositing silicon doped with a second dopant on an inner surface of the high aspect ratio, substantially perpendicular trench, the first cycle comprising alternately depositing silicon at a first constant pressure and etching the deposited silicon at an etching pressure that ramps up from a first value to a second value, the second dopant having a second conductivity type that is opposite from the first conductivity type.