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1.发明授权公开(公告)号：US11515266B2
公开(公告)日：2022-11-29
申请号：US17011982
申请日：2020-09-03
摘要： An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.
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公开(公告)号：US11081390B2
公开(公告)日：2021-08-03
申请号：US16236735
申请日：2018-12-31
IPC分类号： H01L21/768 , H01L23/532
摘要： A method includes electroplate depositing a first metal layer to a first thickness on a metal seed layer, rinsing the first metal layer with deionized water, and after the first rinse process, drying the wafer. The method also includes performing one or more additional electroplating processes that respectively deposit an additional metal layer to a second thickness over the first metal layer, performing an additional rinse process that rinses the additional metal layer with deionized water, and performing an additional drying processes that dries the wafer.
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3.发明申请公开(公告)号：US20180090454A1
公开(公告)日：2018-03-29
申请号：US15820176
申请日：2017-11-21
IPC分类号： H01L23/00 , H01L23/544 , H01L21/66 , H01L21/78 , H01L23/31
摘要： An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.
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4.发明授权公开(公告)号：US09831193B1
公开(公告)日：2017-11-28
申请号：US15169700
申请日：2016-05-31
IPC分类号： H01L23/528 , H01L23/00 , H01L23/544 , H01L23/31 , H01L21/66 , H01L21/78
CPC分类号： H01L23/562 , H01L21/78 , H01L22/32 , H01L23/3192 , H01L23/585 , H01L2223/5446
摘要： An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.
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公开(公告)号：US11508721B2
公开(公告)日：2022-11-22
申请号：US17228631
申请日：2021-04-12
摘要： An integrated circuit has a substrate, a circuit, a core structure, a first encapsulation layer, a second encapsulation layer, and an oxide layer. The circuit includes transistors with active regions developed on the substrate and a metal layer formed above the active regions to provide interconnections for the transistors. The core structure is formed above the metal layer. The first encapsulation layer covers the core structure, and it has a first thermal expansion coefficient. The second encapsulation layer covers the first encapsulation layer over the core structure, and it has a second thermal expansion coefficient that is different from the first thermal expansion coefficient. As a part of the stress relief structure, the oxide layer is formed above the second encapsulation layer. The oxide layer includes an oxide thickness sufficient to mitigate a thermal stress between the first and second encapsulation layers.
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公开(公告)号：US20210327753A1
公开(公告)日：2021-10-21
申请号：US17360271
申请日：2021-06-28
IPC分类号： H01L21/768 , H01L23/532
摘要： Methods of forming metal interconnections of an integrated circuit include electroplating two or more metal layers over a metal seed layer, rinsing each of the metal layers with deionized water after the electroplating, and drying each of the metal layers after the rinsing. After forming a last metal layer, the two or more metal layers are annealed thereby forming a final metal layer, resulting in a low defect density of the final metal layer.
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7.发明授权公开(公告)号：US10770406B2
公开(公告)日：2020-09-08
申请号：US15820176
申请日：2017-11-21
摘要： An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.
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公开(公告)号：US10157861B2
公开(公告)日：2018-12-18
申请号：US15657438
申请日：2017-07-24
IPC分类号： H01L23/544 , H01L23/00 , H01L23/528 , H01L23/532 , H01L23/58 , H01L23/31
摘要： Disclosed embodiments include an integrated circuit having a semiconductor substrate with insulator layers and conductor layers overlying the semiconductor substrate. A scribe region overlying the semiconductor substrate and a periphery of the integrated circuit includes a crack arrest structure and a scribe seal. The crack arrest structure provides first vertical conductor structure that surrounds the periphery of the integrated circuit. The scribe seal is spaced from and surrounded by the crack arrest structure and provides a second vertical conductor structure. The scribe seal includes first and second vias spaced from each other and connected to one of the conductor layers. The first via is a trench via and the second via is a stitch via, with the second via being located closer to the crack arrest structure than the first via.
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公开(公告)号：US20180096784A1
公开(公告)日：2018-04-05
申请号：US15832884
申请日：2017-12-06
IPC分类号： H01F27/34 , G01R33/00 , H01F27/24 , H01L43/12 , H01L23/522 , H01L23/528 , G01R33/04 , H01F27/28
CPC分类号： H01F27/346 , G01R33/0029 , G01R33/04 , H01F27/24 , H01F27/28 , H01L23/5226 , H01L23/528 , H01L27/22 , H01L43/02 , H01L43/12
摘要： An integrated fluxgate device, which includes a magnetic core, an excitation coil, and a sense coil. The magnetic core has a longitudinal edge and a terminal edge. The excitation coil coils around the longitudinal edge of the magnetic core, and the excitation coil has a first number of excitation coil members within a proximity of the terminal edge. The sense coil coils around the longitudinal edge of the magnetic core, and the sense coil has a second number of sense coil members within the proximity of the terminal edge. For reducing fluxgate noise, the second number of sense coil members may be less than the first number of excitation coil members within the proximity of the terminal edge.
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公开(公告)号：US11887888B2
公开(公告)日：2024-01-30
申请号：US17360271
申请日：2021-06-28
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L21/76873 , H01L21/76814 , H01L21/76843 , H01L21/76853 , H01L23/53238
摘要： Methods of forming metal interconnections of an integrated circuit include electroplating two or more metal layers over a metal seed layer, rinsing each of the metal layers with deionized water after the electroplating, and drying each of the metal layers after the rinsing. After forming a last metal layer, the two or more metal layers are annealed thereby forming a final metal layer, resulting in a low defect density of the final metal layer.
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