公开(公告)号：US20250020740A1

公开(公告)日：2025-01-16

申请号：US18903171

申请日：2024-10-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sudtida Lavangkul ,  Sopa Chevacharoenkul

IPC: G01R33/04 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: An integrated fluxgate device includes a substrate that includes a dielectric layer. A fluxgate core is located over the dielectric layer. Lower windings are disposed in a lower metal level between the fluxgate core and the dielectric layer, and upper windings are disposed in an upper metal level above the fluxgate core. A metal structure in the upper metal level or the lower metal level overlaps an end of the fluxgate core and is conductively isolated from the upper and lower windings.

公开(公告)号：US11508721B2

公开(公告)日：2022-11-22

申请号：US17228631

申请日：2021-04-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mona M. Eissa ,  Mark R. Kimmich ,  Sudtida Lavangkul ,  Sopa Chevacharoenkul ,  Mark L. Jenson

IPC: H01L27/06 ,  G01R33/04 ,  G01R33/05

Abstract: An integrated circuit has a substrate, a circuit, a core structure, a first encapsulation layer, a second encapsulation layer, and an oxide layer. The circuit includes transistors with active regions developed on the substrate and a metal layer formed above the active regions to provide interconnections for the transistors. The core structure is formed above the metal layer. The first encapsulation layer covers the core structure, and it has a first thermal expansion coefficient. The second encapsulation layer covers the first encapsulation layer over the core structure, and it has a second thermal expansion coefficient that is different from the first thermal expansion coefficient. As a part of the stress relief structure, the oxide layer is formed above the second encapsulation layer. The oxide layer includes an oxide thickness sufficient to mitigate a thermal stress between the first and second encapsulation layers.

公开(公告)号：US09691751B2

公开(公告)日：2017-06-27

申请号：US14570530

申请日：2014-12-15

Applicant: Texas Instruments Incorporated

Inventor： Bhaskar Srinivasan ,  Khanh Quang Le ,  Collin White ,  Sopa Chevacharoenkul ,  Ashley Norris ,  Bernard John Fischer

IPC: H01L27/02 ,  H01L21/763 ,  H01L29/06

CPC classification number: H01L27/0248 ,  H01L21/763 ,  H01L21/823878 ,  H01L29/0649

Abstract: A method of fabricating an integrated circuit (IC) includes etching a trench in a semiconductor substrate having an aspect ratio (AR) ≧5 and a trench depth ≧10 μm. A dielectric liner is formed along the walls of the trench to form a dielectric lined trench. In-situ doped polysilicon is deposited into the trench to form a dielectric lined polysilicon filled trench having a doped polysilicon filler therein. The doped polysilicon filler after completion of fabricating the IC is essentially polysilicon void-free and has a 25° C. sheet resistance ≦100 ohms/sq. The method can include etching an opening at a bottom of the dielectric liner before depositing the polysilicon to provide ohmic contact to the semiconductor substrate.

公开(公告)号：US11121207B2

公开(公告)日：2021-09-14

申请号：US15348459

申请日：2016-11-10

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Abbas Ali ,  Sopa Chevacharoenkul ,  Jarvis Benjamin Jacobs

IPC: H01L49/02 ,  H01L21/762 ,  H01L21/265 ,  H01L21/308

Abstract: A method for forming trench capacitors includes forming a silicon nitride layer over a first region of a semiconductor surface doped a first type and over a second region doped a second type. A patterned photoresist layer is directly formed on the silicon nitride layer. An etch forms a plurality of deep trenches (DTs) within the first region. A liner oxide is formed that lines the DTs. The silicon nitride layer is etched forming an opening through the silicon nitride layer that is at least as large in area as the area of an opening in the semiconductor surface of the DT below the silicon nitride layer. The liner oxide is removed, a dielectric layer(s) on a surface of the DTs is formed, a top plate material layer is deposited to fill the DTs, and the top plate material layer is removed beyond the DT to form a top plate.

公开(公告)号：US10978448B2

公开(公告)日：2021-04-13

申请号：US15003856

申请日：2016-01-22

Applicant: Texas Instruments Incorporated

Inventor： Mona M. Eissa ,  Mark R. Kimmich ,  Sudtida Lavangkul ,  Sopa Chevacharoenkul ,  Mark L. Jenson

IPC: H01L27/06 ,  G01R33/04 ,  G01R33/05

Abstract: An integrated circuit has a substrate, a circuit, a core structure, a first encapsulation layer, a second encapsulation layer, and an oxide layer. The circuit includes transistors with active regions developed on the substrate and a metal layer formed above the active regions to provide interconnections for the transistors. The core structure is formed above the metal layer. The first encapsulation layer covers the core structure, and it has a first thermal expansion coefficient. The second encapsulation layer covers the first encapsulation layer over the core structure, and it has a second thermal expansion coefficient that is different from the first thermal expansion coefficient. As a part of the stress relief structure, the oxide layer is formed above the second encapsulation layer. The oxide layer includes an oxide thickness sufficient to mitigate a thermal stress between the first and second encapsulation layers.

公开(公告)号：US20170341934A1

公开(公告)日：2017-11-30

申请号：US15680996

申请日：2017-08-18

Applicant: Texas Instruments Incorporated

Inventor： Lee Alan Stringer ,  Mona Eissa ,  Byron J.R. Shulver ,  Sopa Chevacharoenkul ,  Mark R. Kimmich ,  Sudtida Lavangkul ,  Mark L. Jenson

IPC: B81C1/00 ,  G01R33/00 ,  G01R33/04

CPC classification number: B81C1/00825 ,  B81C1/00365 ,  B81C2201/0138 ,  B81C2201/014 ,  G01R33/0047 ,  G01R33/0052 ,  G01R33/04

Abstract: A method comprises forming an etch stop layer, a first titanium layer, a magnetic core, a second titanium layer, and patterning the first and second titanium layers. The etch stop layer is formed above a substrate. The first titanium layer is formed on the etch stop layer. The magnetic core is formed on the first titanium layer. The second titanium layer has a first portion encapsulating the magnetic core with the first titanium layer, and a second portion interfacing with the first titanium layer beyond the magnetic core. The patterning of the first and second titanium layers includes forming a mask over a magnetic core region and etching the first and second titanium layers exposed by the mask using a titanium etchant and a titanium oxide etchant.

公开(公告)号：US20170267521A1

公开(公告)日：2017-09-21

申请号：US15072852

申请日：2016-03-17

Applicant: Texas Instruments Incorporated

Inventor： Lee Alan Stringer ,  Mona Eissa ,  Byron J.R. Shulver ,  Sopa Chevacharoenkul ,  Mark R. Kimmich ,  Sudtida Lavangkul ,  Mark L. Jenson

IPC: B81C1/00 ,  G01R33/04 ,  G01R33/00

CPC classification number: B81C1/00825 ,  B81C1/00365 ,  B81C2201/0138 ,  B81C2201/014 ,  G01R33/0047 ,  G01R33/0052 ,  G01R33/04

Abstract: A method comprises forming an etch stop layer, a first titanium layer, a magnetic core, a second titanium layer, and patterning the first and second titanium layers. The etch stop layer is formed above a substrate. The first titanium layer is formed on the etch stop layer. The magnetic core is formed on the first titanium layer. The second titanium layer has a first portion encapsulating the magnetic core with the first titanium layer, and a second portion interfacing with the first titanium layer beyond the magnetic core. The patterning of the first and second titanium layers includes forming a mask over a magnetic core region and etching the first and second titanium layers exposed by the mask using a titanium etchant and a titanium oxide etchant.

公开(公告)号：US20190331742A1

公开(公告)日：2019-10-31

申请号：US16503660

申请日：2019-07-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sudtida Lavangkul ,  Sopa Chevacharoenkul

IPC: G01R33/04

Abstract: An integrated fluxgate device includes a substrate that includes a dielectric layer. A fluxgate core is located over the dielectric layer. Lower windings are disposed in a lower metal level between the fluxgate core and the dielectric layer, and upper windings are disposed in an upper metal level above the fluxgate core. A metal structure in the upper metal level or the lower metal level overlaps an end of the fluxgate core and is conductively isolated from the upper and lower windings.

公开(公告)号：US09771261B1

公开(公告)日：2017-09-26

申请号：US15072852

申请日：2016-03-17

Applicant: Texas Instruments Incorporated

Inventor： Lee Alan Stringer ,  Mona Eissa ,  Byron J. R. Shulver ,  Sopa Chevacharoenkul ,  Mark R. Kimmich ,  Sudtida Lavangkul ,  Mark L. Jenson

IPC: G01R33/04 ,  B81C1/00 ,  G01R33/00

CPC classification number: B81C1/00825 ,  B81C1/00365 ,  B81C2201/0138 ,  B81C2201/014 ,  G01R33/0047 ,  G01R33/0052 ,  G01R33/04

Abstract: A method comprises forming an etch stop layer, a first titanium layer, a magnetic core, a second titanium layer, and patterning the first and second titanium layers. The etch stop layer is formed above a substrate. The first titanium layer is formed on the etch stop layer. The magnetic core is formed on the first titanium layer. The second titanium layer has a first portion encapsulating the magnetic core with the first titanium layer, and a second portion interfacing with the first titanium layer beyond the magnetic core. The patterning of the first and second titanium layers includes forming a mask over a magnetic core region and etching the first and second titanium layers exposed by the mask using a titanium etchant and a titanium oxide etchant.

公开(公告)号：US12105161B2

公开(公告)日：2024-10-01

申请号：US16503660

申请日：2019-07-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sudtida Lavangkul ,  Sopa Chevacharoenkul

IPC: H10N50/01 ,  G01R33/04 ,  H10N50/80 ,  H10N50/85

CPC classification number: G01R33/04 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: An integrated fluxgate device includes a substrate that includes a dielectric layer. A fluxgate core is located over the dielectric layer. Lower windings are disposed in a lower metal level between the fluxgate core and the dielectric layer, and upper windings are disposed in an upper metal level above the fluxgate core. A metal structure in the upper metal level or the lower metal level overlaps an end of the fluxgate core and is conductively isolated from the upper and lower windings.