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    Integrated fluxgate device
    1.
    发明授权
    Integrated fluxgate device 有权

    公开(公告)号：US11508721B2

    公开(公告)日：2022-11-22

    申请号：US17228631

    申请日：2021-04-12

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mona M. Eissa ,  Mark R. Kimmich ,  Sudtida Lavangkul ,  Sopa Chevacharoenkul ,  Mark L. Jenson

    IPC: H01L27/06 ,  G01R33/04 ,  G01R33/05

    Abstract: An integrated circuit has a substrate, a circuit, a core structure, a first encapsulation layer, a second encapsulation layer, and an oxide layer. The circuit includes transistors with active regions developed on the substrate and a metal layer formed above the active regions to provide interconnections for the transistors. The core structure is formed above the metal layer. The first encapsulation layer covers the core structure, and it has a first thermal expansion coefficient. The second encapsulation layer covers the first encapsulation layer over the core structure, and it has a second thermal expansion coefficient that is different from the first thermal expansion coefficient. As a part of the stress relief structure, the oxide layer is formed above the second encapsulation layer. The oxide layer includes an oxide thickness sufficient to mitigate a thermal stress between the first and second encapsulation layers.

    Integrated fluxgate device
    3.
    发明授权
    Integrated fluxgate device 有权

    公开(公告)号：US10978448B2

    公开(公告)日：2021-04-13

    申请号：US15003856

    申请日：2016-01-22

    Applicant: Texas Instruments Incorporated

    Inventor： Mona M. Eissa ,  Mark R. Kimmich ,  Sudtida Lavangkul ,  Sopa Chevacharoenkul ,  Mark L. Jenson

    IPC: H01L27/06 ,  G01R33/04 ,  G01R33/05

    Abstract: An integrated circuit has a substrate, a circuit, a core structure, a first encapsulation layer, a second encapsulation layer, and an oxide layer. The circuit includes transistors with active regions developed on the substrate and a metal layer formed above the active regions to provide interconnections for the transistors. The core structure is formed above the metal layer. The first encapsulation layer covers the core structure, and it has a first thermal expansion coefficient. The second encapsulation layer covers the first encapsulation layer over the core structure, and it has a second thermal expansion coefficient that is different from the first thermal expansion coefficient. As a part of the stress relief structure, the oxide layer is formed above the second encapsulation layer. The oxide layer includes an oxide thickness sufficient to mitigate a thermal stress between the first and second encapsulation layers.

    Integrated Fluxgate Device
    6.
    发明申请
    Integrated Fluxgate Device 有权

    公开(公告)号：US20210233903A1

    公开(公告)日：2021-07-29

    申请号：US17228631

    申请日：2021-04-12

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mona M. Eissa ,  Mark R. Kimmich ,  Sudtida Lavangkul ,  Sopa Chevacharoenkul ,  Mark L. Jenson

    IPC: H01L27/06 ,  G01R33/04 ,  G01R33/05

    Abstract: An integrated circuit has a substrate, a circuit, a core structure, a first encapsulation layer, a second encapsulation layer, and an oxide layer. The circuit includes transistors with active regions developed on the substrate and a metal layer formed above the active regions to provide interconnections for the transistors. The core structure is formed above the metal layer. The first encapsulation layer covers the core structure, and it has a first thermal expansion coefficient. The second encapsulation layer covers the first encapsulation layer over the core structure, and it has a second thermal expansion coefficient that is different from the first thermal expansion coefficient. As a part of the stress relief structure, the oxide layer is formed above the second encapsulation layer. The oxide layer includes an oxide thickness sufficient to mitigate a thermal stress between the first and second encapsulation layers.

    Integrated Fluxgate Device
    8.
    发明申请
    Integrated Fluxgate Device 审中-公开

    公开(公告)号：US20170213956A1

    公开(公告)日：2017-07-27

    申请号：US15003856

    申请日：2016-01-22

    Applicant: Texas Instruments Incorporated

    Inventor： Mona M. Eissa ,  Mark R. Kimmich ,  Sudtida Lavangkul ,  Sopa Chevacharoenkul ,  Mark L. Jenson

    IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

    CPC classification number: H01L27/0617 ,  G01R33/04 ,  G01R33/05

    Abstract: An integrated circuit has a substrate, a circuit, a core structure, a first encapsulation layer, a second encapsulation layer, and an oxide layer. The circuit includes transistors with active regions developed on the substrate and a metal layer formed above the active regions to provide interconnections for the transistors. The core structure is formed above the metal layer. The first encapsulation layer covers the core structure, and it has a first thermal expansion coefficient. The second encapsulation layer covers the first encapsulation layer over the core structure, and it has a second thermal expansion coefficient that is different from the first thermal expansion coefficient. As a part of the stress relief structure, the oxide layer is formed above the second encapsulation layer. The oxide layer includes an oxide thickness sufficient to mitigate a thermal stress between the first and second encapsulation layers.

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