RESISTOR WITH EXPONENTIAL-WEIGHTED TRIM
    2.
    发明申请

    公开(公告)号:US20200075573A1

    公开(公告)日:2020-03-05

    申请号:US16547615

    申请日:2019-08-22

    IPC分类号: H01L27/00 H01L23/525

    摘要: An electronic device, e.g. a trimmable resistor, includes a plurality of fused resistors, each fused resistor including one or more doped resistive regions formed in a semiconductor substrate. The doped resistive regions may be thermistors. Each fused resistor further includes a corresponding one of a plurality of fusible links. A first terminal of each of the fused resistors is connected to a first terminal of the corresponding fusible link. First and second interconnection buses are located over the substrate, with the first interconnection bus connecting to a second terminal of each of the fused resistors, and the second interconnection bus connecting to a second terminal of each of the fusible links. The plurality of fused resistors have resistance values that form an exponential progression.

    METHODS AND APPARATUS FOR SCRIBE STREET PROBE PADS WITH REDUCED DIE CHIPPING DURING WAFER DICING

    公开(公告)号:US20210217706A1

    公开(公告)日:2021-07-15

    申请号:US17011982

    申请日:2020-09-03

    摘要: An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.

    Fluxgate device with low fluxgate noise
    7.
    发明授权
    Fluxgate device with low fluxgate noise 有权
    磁通门装置磁通门噪声低

    公开(公告)号:US09577185B1

    公开(公告)日:2017-02-21

    申请号:US15141003

    申请日:2016-04-28

    摘要: An integrated fluxgate device, which includes a magnetic core, an excitation coil, and a sense coil. The magnetic core has a longitudinal edge and a terminal edge. The excitation coil coils around the longitudinal edge of the magnetic core, and the excitation coil has a first number of excitation coil members within a proximity of the terminal edge. The sense coil coils around the longitudinal edge of the magnetic core, and the sense coil has a second number of sense coil members within the proximity of the terminal edge. For reducing fluxgate noise, the second number of sense coil members may be less than the first number of excitation coil members within the proximity of the terminal edge.

    摘要翻译: 集成磁通门装置,其包括磁芯,励磁线圈和感测线圈。 磁芯具有纵向边缘和末端边缘。 励磁线圈围绕磁芯的纵向边缘缠绕,并且励磁线圈在端子边缘附近具有第一数量的励磁线圈构件。 感测线圈围绕磁芯的纵向边缘缠绕,并且感测线圈在端子边缘附近具有第二数量的感测线圈构件。 为了减小磁通门噪声,第二数量的感测线圈构件可以小于在端子边缘附近的第一数量的励磁线圈构件。

    RESISTOR WITH EXPONENTIAL-WEIGHTED TRIM

    公开(公告)号:US20210343694A1

    公开(公告)日:2021-11-04

    申请号:US17376747

    申请日:2021-07-15

    摘要: An electronic device, e.g. a trimmable resistor, includes a plurality of fused resistors, each fused resistor including one or more doped resistive regions formed in a semiconductor substrate. The doped resistive regions may be thermistors. Each fused resistor further includes a corresponding one of a plurality of fusible links. A first terminal of each of the fused resistors is connected to a first terminal of the corresponding fusible link. First and second interconnection buses are located over the substrate, with the first interconnection bus connecting to a second terminal of each of the fused resistors, and the second interconnection bus connecting to a second terminal of each of the fusible links. The plurality of fused resistors have resistance values that form an exponential progression.

    Methods and apparatus for scribe street pads with reduced die chipping during wafer dicing

    公开(公告)号:US10770406B2

    公开(公告)日:2020-09-08

    申请号:US15820176

    申请日:2017-11-21

    摘要: An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.