-
公开(公告)号:US20190341917A1
公开(公告)日:2019-11-07
申请号:US15969034
申请日:2018-05-02
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Xiong LI , Toru TANAKA
Abstract: A system comprises a gate driver that is configured to couple to a transistor disposed in a transistor module via a first pin. The gate driver comprises a duty cycle measurement circuit having a first input terminal and a first output terminal, the first input terminal coupled to a second pin via an isolator. The duty cycle measurement circuit comprises a flip-flop, a counter, a shift register, and a comparator. The system comprises an analog to digital converter circuit having a second input terminal, a second output terminal, and a reference terminal, the second input terminal coupled to a third pin configured to couple to a temperature-sensitive device disposed in the transistor module, the second output terminal coupled to a fourth pin via the isolator, and the reference terminal coupled to the first output terminal.
-
公开(公告)号:US20200096574A1
公开(公告)日:2020-03-26
申请号:US16137146
申请日:2018-09-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Xiong LI , William TOTH , Honglin GUO , Danyang ZHU
Abstract: A device that comprises a first semiconductor die and a second semiconductor die. The first semiconductor die comprises a first clock signal generator. The second semiconductor die comprises a fault detection circuit, the fault detection circuit comprising a second clock signal generator, a first counter coupled to the second clock signal generator, multiple storage devices coupled to the second clock signal generator and to the first counter, a logic gate coupled to the multiple storage devices, a second counter coupled to the logic gate and to the first clock signal generator, and a comparator coupled to the logic gate and the second counter.
-
公开(公告)号:US20180343009A1
公开(公告)日:2018-11-29
申请号:US15854515
申请日:2017-12-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Xiong LI , Toru TANAKA
IPC: H03K19/0952 , H02M7/537 , H03K17/06 , H03K17/22 , H03K5/19 , H03K19/017
CPC classification number: H03K19/0952 , H02M7/537 , H03K5/19 , H03K17/063 , H03K17/223 , H03K19/01707
Abstract: A gate driver includes a drive signal input terminal, a drive signal output terminal, a gate drive circuit, and a serial communication interface. The drive signal input terminal is configured to receive a gate drive signal. The gate drive circuit is coupled to the drive signal input terminal and the drive signal output terminal. The gate drive circuit is configured to provide the gate drive signal to the drive signal output terminal. The serial communication interface is coupled to the drive signal input terminal.
-
-