公开(公告)号：US20240421825A1

公开(公告)日：2024-12-19

申请号：US18821218

申请日：2024-08-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： BICHOY BAHR ,  YOGESH RAMADASS

IPC: H03L7/099 ,  H03B5/32 ,  H03H9/02 ,  H03K3/0231 ,  H03L7/085 ,  H03M1/46

Abstract: In one example, an apparatus comprises an oscillator having a control input and a clock output. The apparatus also comprises a frequency control circuit having an input and a control output, the control output coupled to the control input, and a reference clock generator having a reference clock output. The apparatus also comprises a multiplexer having a first multiplexer input, a second multiplexer input, a selection input, and a multiplexer output, the first multiplexer input coupled to the clock output, the second multiplexer input coupled to the reference clock output, and the multiplexer output coupled to the input of the frequency control circuit.

公开(公告)号：US20240113717A1

公开(公告)日：2024-04-04

申请号：US17936505

申请日：2022-09-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： BICHOY BAHR ,  YOGESH RAMADASS

IPC: H03L7/099 ,  H03B5/32 ,  H03H9/02 ,  H03K3/0231 ,  H03L7/085 ,  H03M1/46

CPC classification number: H03L7/0995 ,  H03B5/326 ,  H03H9/02244 ,  H03K3/0231 ,  H03L7/085 ,  H03M1/46

Abstract: A clock circuit includes a voltage-controlled oscillator (VCO) having a control input and a first clock output. The clock circuit includes a frequency-locked loop (FLL) having an FLL input and a control output, the control output coupled to the control input. A microelectromechanical system (MEMS) resonator-based oscillator has a second clock output. A multiplexer has a first multiplexer input, a second multiplexer input, a selection input, and a multiplexer output. The first multiplexer input is coupled to the first clock output. The second multiplexer input is coupled to the second clock output. The multiplexer output is coupled to the FLL input.