公开(公告)号：US20170345778A1

公开(公告)日：2017-11-30

申请号：US15527666

申请日：2015-11-18

Applicant: THALES

Inventor： Patrick GREMILLET ,  Bernard LEDAIN

IPC: H01L23/60 ,  H01L23/498 ,  H01L23/31 ,  H05K3/34 ,  H05K1/02

CPC classification number: H01L23/60 ,  H01L23/053 ,  H01L23/3114 ,  H01L23/3677 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49833 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H05K1/0243 ,  H05K3/3436 ,  H05K2201/0999 ,  H05K2201/10454 ,  Y02P70/613 ,  H01L2224/45099

Abstract: A package, able to encapsulate at least one component, forming a closed cavity of Faraday cage type having side walls resting on a base and that are surmounted by a cover, wherein at least one of the side walls includes exterior electrical connection elements linked electrically to the interior of the cavity, the exterior connection elements able to interconnect with an exterior circuit such that the side wall faces the exterior circuit when the exterior connection elements are interconnected with the circuit.

公开(公告)号：US20160148706A1

公开(公告)日：2016-05-26

申请号：US14889813

申请日：2014-05-14

Applicant: THALES

Inventor： Patrick GREMILLET

IPC: G11C27/02

CPC classification number: G11C27/024

Abstract: The sample-and-hold device comprises a holding capacitor and operates according to a track phase during which the voltage on the terminals of the capacitor tracks the input signal and according to a hold phase during which the capacitor is isolated from the input signal, it comprises: a differential pair comprising a first transistor Q1 and a second transistor Q2 connected as common emitters, the collector of the transistor Q2 being connected to the holding capacitor, the input signal being applied to the base of the transistor Q1; a third transistor Q3, of which the base is connected to the collector of the transistor Q2 and the emitter is connected to the base of the transistor Q2, the signal present on the emitter of the transistor Q3 forming the output signal of the sample-and-hold device; a current source I connected to the collector of the transistor Q2; during the track phase, the differential pair Q1, Q2 being supplied by a current 2I, the transistor Q2 being charged by the current source and by the holding capacitor, during the hold phase, the current 2I supplying the differential pair Q1, Q2 being disconnected and the holding capacitor being charged by two opposite currents having the same value, equal to the current I of the source.

Abstract translation: 采样和保持装置包括保持电容器，并根据磁道相位进行操作，在该阶段期间，电容器端子上的电压跟踪输入信号，并且根据电容器与输入信号隔离的保持相位， 包括：包括作为公共发射极连接的第一晶体管Q1和第二晶体管Q2的差分对，晶体管Q2的集电极连接到保持电容器，输入信号施加到晶体管Q1的基极; 第三晶体管Q3，其基极连接到晶体管Q2的集电极，发射极连接到晶体管Q2的基极，存在于晶体管Q3的发射极上的信号形成样品的输出信号，以及 固定装置 连接到晶体管Q2的集电极的电流源I; 在跟踪期间，差动对Q1，Q2由电流2I提供，晶体管Q2由电流源和保持电容充电，在保持阶段期间，提供差动对Q1，Q2的电流2I断开 并且保持电容器由具有相同值的两个相反电流充电，等于源极的电流I.