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公开(公告)号:US20150318401A1
公开(公告)日:2015-11-05
申请号:US14654164
申请日:2013-12-20
Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
Inventor: Xiangfeng Duan , Woojong Yu , Yuan Liu , Yu Huang
IPC: H01L29/786 , H01L31/0224 , H01L31/113 , H01L31/032 , H01L29/417 , H01L29/45
CPC classification number: H01L29/7869 , H01L29/1606 , H01L29/41733 , H01L29/41775 , H01L29/45 , H01L29/66742 , H01L29/66969 , H01L29/78642 , H01L29/78681 , H01L29/78684 , H01L29/78693 , H01L29/78696 , H01L31/022408 , H01L31/032 , H01L31/113
Abstract: A vertically stacked heterostructure device includes: (1) a substrate; and (2) vertically stacked layers disposed over the substrate and including (a) a source electrode including a layer of graphene; (b) a drain electrode; and (c) a semiconducting channel disposed between the source electrode and the drain electrode. During operation of the device, a current is configured to flow between the source electrode and the drain electrode through the semiconducting channel.
Abstract translation: 垂直堆叠的异质结构器件包括:(1)衬底; 和(2)设置在所述衬底上的垂直堆叠层,并且包括(a)包括石墨烯层的源电极; (b)漏电极; 和(c)设置在源电极和漏电极之间的半导体沟道。 在器件工作期间,电流被配置为通过半导体通道在源电极和漏电极之间流动。
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公开(公告)号:US09685559B2
公开(公告)日:2017-06-20
申请号:US14654164
申请日:2013-12-20
Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
Inventor: Xiangfeng Duan , Woojong Yu , Yuan Liu , Yu Huang
IPC: H01L29/786 , H01L29/417 , H01L29/45 , H01L31/113 , H01L31/032 , H01L31/0224 , H01L29/16 , H01L29/66
CPC classification number: H01L29/7869 , H01L29/1606 , H01L29/41733 , H01L29/41775 , H01L29/45 , H01L29/66742 , H01L29/66969 , H01L29/78642 , H01L29/78681 , H01L29/78684 , H01L29/78693 , H01L29/78696 , H01L31/022408 , H01L31/032 , H01L31/113
Abstract: A vertically stacked heterostructure device includes: (1) a substrate; and (2) vertically stacked layers disposed over the substrate and including (a) a source electrode including a layer of graphene; (b) a drain electrode; and (c) a semiconducting channel disposed between the source electrode and the drain electrode. During operation of the device, a current is configured to flow between the source electrode and the drain electrode through the semiconducting channel.
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