公开(公告)号：US20160336334A1

公开(公告)日：2016-11-17

申请号：US15222092

申请日：2016-07-28

Applicant: THIN FILM ELECTRONICS ASA

Inventor： Christer Karlsson ,  Olle Jonny Hagel ,  Jakob Nilsson ,  Per Bröms

IPC: H01L27/115 ,  H01L27/02 ,  H01L49/02

CPC classification number: H01L27/11507 ,  G11B9/02 ,  G11C11/161 ,  G11C11/22 ,  H01L23/562 ,  H01L27/0248 ,  H01L27/11502 ,  H01L27/1203 ,  H01L28/40 ,  H01L28/55 ,  H01L28/75 ,  H01L43/02 ,  H01L43/12 ,  H01L51/0591 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A ferroelectric memory cell (1) and a memory device (100) comprising one or more such cells (1). The ferroelectric memory cell comprises a stack (4) of layers arranged on a flexible substrate (3). Said stack comprises an electrically active part (4a) and a protective layer (11) for protecting the electrically active part against scratches and abrasion. Said electrically active part comprises a bottom electrode layer (5) and a top electrode layer (9) and at least one ferroelectric memory material layer (7) between said electrodes. The stack further comprises a buffer layer (13) arranged between the top electrode layer (9) and the protective layer (11). The buffer layer (13) is adapted for at least partially absorbing a lateral dimensional change (ΔL) occurring in the protective layer (11) and thus preventing said dimensional change (ΔL) from being transferred to the electrically active part (4a), thereby reducing the risk of short circuit to occur between the electrodes.

Abstract translation: 铁电存储器单元（1）和包括一个或多个这样的单元（1）的存储器件（100）。 铁电存储单元包括布置在柔性基板（3）上的层叠层（4）。 所述堆叠包括电活性部分（4a）和保护层（11），用于保护电活性部分免受划伤和磨损。 所述电活性部分包括底电极层（5）和顶电极层（9）和在所述电极之间的至少一个铁电存储材料层（7）。 该堆叠还包括布置在顶部电极层（9）和保护层（11）之间的缓冲层（13）。 缓冲层（13）适于至少部分地吸收出现在保护层（11）中的横向尺寸变化（ΔL），从而防止所述尺寸变化（ΔL）转移到电活性部分（4a），由此 降低在电极之间发生短路的风险。

公开(公告)号：US10453853B2

公开(公告)日：2019-10-22

申请号：US15222092

申请日：2016-07-28

Applicant: THIN FILM ELECTRONICS ASA

Inventor： Christer Karlsson ,  Olle Jonny Hagel ,  Jakob Nilsson ,  Per Bröms

IPC: H01L27/115 ,  H01L27/11507 ,  G11B9/02 ,  H01L27/11502 ,  H01L51/05 ,  H01L27/12 ,  H01L49/02 ,  G11C11/16 ,  H01L23/00 ,  H01L43/02 ,  H01L43/12 ,  H01L27/02 ,  G11C11/22

Abstract: A ferroelectric memory cell (1) and a memory device (100) comprising one or more such cells (1). The ferroelectric memory cell comprises a stack (4) of layers arranged on a flexible substrate (3). Said stack comprises an electrically active part (4a) and a protective layer (11) for protecting the electrically active part against scratches and abrasion. Said electrically active part comprises a bottom electrode layer (5) and a top electrode layer (9) and at least one ferroelectric memory material layer (7) between said electrodes. The stack further comprises a buffer layer (13) arranged between the top electrode layer (9) and the protective layer (11). The buffer layer (13) is adapted for at least partially absorbing a lateral dimensional change (ΔL) occurring in the protective layer (11) and thus preventing said dimensional change (ΔL) from being transferred to the electrically active part (4a), thereby reducing the risk of short circuit to occur between the electrodes.