-
公开(公告)号:US20200286828A1
公开(公告)日:2020-09-10
申请号:US16564584
申请日:2019-09-09
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Keiji HOSOTANI , Fumitaka ARAI , Keisuke NAKATSUKA , Nobuyuki MOMO , Motohiko FUJIMATSU
IPC: H01L23/528 , H01L27/1157 , H01L27/11582 , H01L27/11565 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L23/522
Abstract: According to one embodiment, a semiconductor memory device includes: a first semiconductor layer including first to third portions which are arranged along a first direction and differ in position from one another in a second direction; a conductive layer including a fourth portion extending in the second direction and a fifth portion extending in the first direction; a first insulating layer between the fourth portion and the first semiconductor layer and between the fifth portion and the first semiconductor layer; a first contact plug coupled to the fourth portion; a second contact plug coupled to the first semiconductor layer in a region where the first insulating layer is formed; a first interconnect; and a first memory cell apart from the fifth portion in the first direction and storing information between the semiconductor layer and the first interconnect.
-
公开(公告)号:US20200098829A1
公开(公告)日:2020-03-26
申请号:US16289651
申请日:2019-02-28
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Yusuke ARAYASHIKI , Nobuyuki MOMO , Motohiko FUJIMATSU , Akira HOKAZONO
IPC: H01L27/24
Abstract: A storage device includes: a substrate; a first conductive layer extending in a first direction; a second conductive layer adjacent to the first conductive layer in a second direction, and extending in the first direction; a third conductive layer extending in a third direction; a fourth conductive layer extending in the second direction; a fifth conductive layer disposed on the second conductive layer, extending in the third direction, and being electrically connected to the fourth conductive layer; a first storage layer disposed between the third conductive layer and the fourth conductive layer; a first semiconductor layer disposed between the first conductive layer and the third conductive layer; a second semiconductor layer disposed between the second conductive layer and the fifth conductive layer; and a first gate electrode extending in the second direction and being shared by side surfaces of the first semiconductor layer and the second semiconductor layer.
-