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    MEMORY DEVICE
    2.
    发明申请
    MEMORY DEVICE 审中-公开

    公开(公告)号：US20180277183A1

    公开(公告)日：2018-09-27

    申请号：US15702430

    申请日：2017-09-12

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Keiji HOSOTANI ,  Tatsuya KISHI ,  Akira KATAYAMA

    IPC: G11C11/16 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10

    CPC classification number: G11C11/161 ,  G11C11/1673 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10

    Abstract: According to one embodiment, a memory includes a first MTJ element having a first area along a first plane; and second MTJ elements each having a second area along the first plane. The second area is larger than or equal to twice the first area and smaller than or equal to five times the first area. Each of the second MTJ elements includes a first ferromagnet, a second ferromagnet, and a first nonmagnet. Respective magnetizations of respective first ferromagnets of the second MTJ elements are oriented along a first direction. Respective magnetizations of respective second ferromagnets of the second MTJ elements are oriented along a second direction. One of the second MTJ elements is coupled to another one of the second MTJ elements in series or in parallel.

    SEMICONDUCTOR MEMORY DEVICE
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20200303400A1

    公开(公告)日：2020-09-24

    申请号：US16502877

    申请日：2019-07-03

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Fumitaka ARAI ,  Masakazu GOTO ,  Masaki KONDO ,  Keiji HOSOTANI ,  Nobuyuki MOMO

    IPC: H01L27/11582 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  H01L27/1157 ,  H01L27/11573

    Abstract: According to one embodiment, a semiconductor memory device includes: a first interconnecting layer; a first signal line; a first memory cell that stores first information between the first interconnecting layer and the first signal line; second to fourth interconnecting layers provided above the first interconnecting layer; fifth to seventh interconnecting layers disposed apart from the second to fourth interconnecting layers; a second signal line coupled to the first signal line; a third signal line coupled to the first and second signal lines and the sixth interconnecting layer; and, first to fifth transistors.

    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20200286828A1

    公开(公告)日：2020-09-10

    申请号：US16564584

    申请日：2019-09-09

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Keiji HOSOTANI ,  Fumitaka ARAI ,  Keisuke NAKATSUKA ,  Nobuyuki MOMO ,  Motohiko FUJIMATSU

    IPC: H01L23/528 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L23/522

    Abstract: According to one embodiment, a semiconductor memory device includes: a first semiconductor layer including first to third portions which are arranged along a first direction and differ in position from one another in a second direction; a conductive layer including a fourth portion extending in the second direction and a fifth portion extending in the first direction; a first insulating layer between the fourth portion and the first semiconductor layer and between the fifth portion and the first semiconductor layer; a first contact plug coupled to the fourth portion; a second contact plug coupled to the first semiconductor layer in a region where the first insulating layer is formed; a first interconnect; and a first memory cell apart from the fifth portion in the first direction and storing information between the semiconductor layer and the first interconnect.

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