公开(公告)号：US20190295639A1

公开(公告)日：2019-09-26

申请号：US16113838

申请日：2018-08-27

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Shingo NAKAZAWA ,  Takayuki MIYAZAKI

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell having a variable resistance unit, a first selector, and a second selector. The first and second selectors are connected in series with the variable resistance unit and have different switching characteristics from one another. A control unit is provided to write data to the memory cell by setting a resistance state of the variable resistance unit and to read data from the memory cell according to the resistance state of the variable resistance unit.

公开(公告)号：US20190081101A1

公开(公告)日：2019-03-14

申请号：US15905256

申请日：2018-02-26

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Shingo NAKAZAWA ,  Tsuneo INABA ,  Hiroyuki TAKENAKA

IPC: H01L27/22 ,  H01L27/24 ,  G11C13/00

CPC classification number: H01L27/222 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/79 ,  G11C2213/81 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2481

Abstract: A semiconductor memory device includes memory cell arrays that include a plurality of memory cells. A first control circuit with control transistors of a first conductivity type is in a first region below the memory cell arrays. A second control circuit includes a first transistor of a first conductivity type connected in parallel to a second transistor of a second conductivity type. one of the first and second transistors is connected to an end of at least one control transistor. The second control circuit delivers a voltage to the plurality of control transistors. The first transistor is disposed in the first region. The second transistor is disposed in a second region adjacent to the first region. The second region is below a gap between adjacent memory cell arrays.

公开(公告)号：US20200294585A1

公开(公告)日：2020-09-17

申请号：US16557818

申请日：2019-08-30

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Shingo NAKAZAWA

IPC: G11C13/00 ,  H01L23/528 ,  H01L27/24 ,  H01L45/00

Abstract: A semiconductor storage device includes interconnections in a first layer and a second layer, a first memory cell between a first and a second interconnection, and a dummy memory cell between the first interconnection and a third interconnection. A controller applies a first voltage of a first polarity to the first interconnection and a second voltage of a second polarity opposite the first polarity to the second interconnection at a first time. The controller applies a third voltage at a second time after the first time to the first interconnection. The third voltage having a smaller magnitude smaller than first voltage. The controller applies a fourth voltage to the third interconnection at the second time. The fourth voltage has a magnitude larger than the third voltage but smaller than the first voltage.