公开(公告)号：US20200091173A1

公开(公告)日：2020-03-19

申请号：US16281334

申请日：2019-02-21

Applicant: Toshiba Memory Corporation

Inventor： Osamu MIYAGAWA ,  Takahiro TOMIMATSU

IPC: H01L27/11582 ,  H01L21/311

Abstract: A semiconductor device according to one embodiment includes a semiconductor substrate and a stack body including first films and second films alternately stacked in a first direction perpendicular to the semiconductor substrate, and including a stepped end portion. Each of the first films has a thick film portion located on the end portion, and an eave portion hanging over from a upper part of the thick film portion to the side in a second direction parallel to the semiconductor substrate.

公开(公告)号：US20190088672A1

公开(公告)日：2019-03-21

申请号：US15890894

申请日：2018-02-07

Applicant: Toshiba Memory Corporation

Inventor： Takahiro TOMIMATSU

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/00

Abstract: According to one embodiment, a multi-layer wiring structure includes a first multi-layer section, first contact plugs, and pillars. First conductors and first insulators are alternately layered in the first multi-layer section. The multi-layer section includes a first area that includes memory cells, and a second area different from the first area. The first contact plugs are formed in the first holes extending from an uppermost layer of the first multi-layer section respectively to the first conductors in the second area, side surfaces of the first contact plugs being covered with first insulating films. The pillars are formed of second insulators and passing through the first multi-layer section in a layered direction in the second area.

公开(公告)号：US20200286990A1

公开(公告)日：2020-09-10

申请号：US16510488

申请日：2019-07-12

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yasuhiro UCHIYAMA ,  Shinya ARAI ,  Koichi SAKATA ,  Takahiro TOMIMATSU

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/761

Abstract: A semiconductor device including a first chip and a second chip. The first chip includes: a first substrate; a first transistor that is provided on the first substrate; and a first pad that is provided above the first transistor and that is electrically connected to the first transistor. The second chip includes: a second pad that is provided on the first pad; a second substrate that is provided above the second pad and that includes a first diffusion layer and a second diffusion layer, at least one of the first diffusion layer and the second diffusion layer being electrically connected to the second pad; and an isolation insulating film or an isolation trench that extends at least from an upper surface of the second substrate to a lower surface of the second substrate within the second substrate and that isolates the first diffusion layer from the second diffusion layer.

公开(公告)号：US20190214268A1

公开(公告)日：2019-07-11

申请号：US16126055

申请日：2018-09-10

Applicant: Toshiba Memory Corporation

Inventor： Masakazu SAWANO ,  Takahiro TOMIMATSU ,  Junichi SHIBATA ,  Hideki INOKUMA ,  Hisashi KATO ,  Kenta YOSHINAGA

IPC: H01L21/311 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582

Abstract: According to one embodiment, a semiconductor device includes: a first stack above a substrate and including insulation layers and conductive layers alternately stacked in a first direction, the first stack including a staircase-shaped portion in an end portion of the first stack in a second direction parallel to a main face of the substrate, the staircase-shaped portion including steps and terraces corresponding to the conductive layers, at least a part of the steps having arc shape curved along a third direction crossing the second direction; and a second stack above the substrate and including first and second layers stacked in the first direction. In the second and/or third direction, a dimension of the first stack is larger than a dimension of the second stack.