公开(公告)号：US20200286990A1

公开(公告)日：2020-09-10

申请号：US16510488

申请日：2019-07-12

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yasuhiro UCHIYAMA ,  Shinya ARAI ,  Koichi SAKATA ,  Takahiro TOMIMATSU

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/761

Abstract: A semiconductor device including a first chip and a second chip. The first chip includes: a first substrate; a first transistor that is provided on the first substrate; and a first pad that is provided above the first transistor and that is electrically connected to the first transistor. The second chip includes: a second pad that is provided on the first pad; a second substrate that is provided above the second pad and that includes a first diffusion layer and a second diffusion layer, at least one of the first diffusion layer and the second diffusion layer being electrically connected to the second pad; and an isolation insulating film or an isolation trench that extends at least from an upper surface of the second substrate to a lower surface of the second substrate within the second substrate and that isolates the first diffusion layer from the second diffusion layer.

公开(公告)号：US20190333928A1

公开(公告)日：2019-10-31

申请号：US16298865

申请日：2019-03-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Satoshi NAGASHIMA ,  Keisuke NAKATSUKA ,  Fumitaka ARAI ,  Shinya ARAI ,  Yasuhiro UCHIYAMA

IPC: H01L27/11578 ,  H01L27/1157 ,  G11C11/40

Abstract: According to one embodiment, a semiconductor memory device includes: first and second signal lines; a first memory cell storing first information by applying voltage across the first signal line and a first interconnect layer; a second memory cell storing second information by applying voltage across the second signal line and a second interconnect layer; a first conductive layer provided on the first and second signal lines; third and fourth signal lines provided on the first conductive layer; a third memory cell storing third information by applying voltage across the third signal line and a third interconnect layer; and a fourth memory cell storing fourth information by applying voltage across the fourth signal line and a fourth interconnect layer.

公开(公告)号：US20200075625A1

公开(公告)日：2020-03-05

申请号：US16293954

申请日：2019-03-06

Applicant: Toshiba Memory Corporation

Inventor： Shigeki KOBAYASHI ,  Masaru KITO ,  Yasuhiro UCHIYAMA

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/10 ,  H01L27/11573 ,  H01L23/528

Abstract: A semiconductor memory device includes: a first conductive layer and a first insulating layer extending in a first direction, these layers being arranged in a second direction intersecting the first direction; a first semiconductor layer opposed to the first conductive layer, and extending in a third direction intersecting the first and second directions; a second semiconductor layer opposed to the first conductive layer, extending in the third direction; a first contact electrode connected to the first semiconductor layer; and a second contact electrode connected to the second semiconductor layer. In a first cross section extending in the first and second directions, an entire outer peripheral surface of the first semiconductor layer is surrounded by the first conductive layer, and an outer peripheral surface of the second semiconductor layer is surrounded by the first conductive layer and the first insulating layer.

公开(公告)号：US20190296037A1

公开(公告)日：2019-09-26

申请号：US16114045

申请日：2018-08-27

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yasuhiro UCHIYAMA

IPC: H01L27/11582 ,  H01L29/423 ,  H01L27/1157

Abstract: A semiconductor memory device includes a substrate; a stacked body on the substrate and including a first stacked body formed of stacked first electrode layers and a second stacked body on the first stacked body and including a second electrode layer; a hole passing through the stacked bodies in a first direction and having a first insulator, and a channel film between the first insulator and first electrode layers and between the first insulator and second electrode layer and having first and second portions facing each other, with the first insulator placed therebetween. A first memory between the first electrode layers and the first portion and a second memory between the first electrode layers and the second portion are insulated. A third memory between the second electrode layer and the first portion and a fourth memory between the second electrode layer and the second portion are connected.