公开(公告)号：US20170373080A1

公开(公告)日：2017-12-28

申请号：US15677361

申请日：2017-08-15

Applicant: Toshiba Memory Corporation

Inventor： Yoshihiro AKUTSU ,  Ryota KATSUMATA

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L21/768 ,  H01L21/74 ,  H01L27/1157 ,  H01L23/535 ,  H01L27/11573 ,  H01L27/11578

CPC classification number: H01L27/11556 ,  H01L21/743 ,  H01L21/76889 ,  H01L23/535 ,  H01L25/00 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.

公开(公告)号：US20200350327A1

公开(公告)日：2020-11-05

申请号：US16932189

申请日：2020-07-17

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yoshihiro AKUTSU ,  Ryota KATSUMATA

IPC: H01L27/11556 ,  H01L21/768 ,  H01L21/74 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11578 ,  H01L23/535 ,  H01L27/11573 ,  H01L25/00

Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.

公开(公告)号：US20190074284A1

公开(公告)日：2019-03-07

申请号：US16176634

申请日：2018-10-31

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yoshihiro AKUTSU ,  Ryota KATSUMATA

IPC: H01L27/11556 ,  H01L25/00 ,  H01L27/11573 ,  H01L27/1157 ,  H01L21/74 ,  H01L21/768 ,  H01L23/535 ,  H01L27/11582 ,  H01L27/11578

CPC classification number: H01L27/11556 ,  H01L21/743 ,  H01L21/76889 ,  H01L23/535 ,  H01L25/00 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of theNAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.