公开(公告)号：US07944239B2

公开(公告)日：2011-05-17

申请号：US11780419

申请日：2007-07-19

申请人： Ta Lee Yu ,  Hai Feng Xue ,  Hui Juan Cheng

发明人： Ta Lee Yu ,  Hai Feng Xue ,  Hui Juan Cheng

IPC分类号： H03K19/094

CPC分类号： G06F13/4081

摘要： System and method for providing live insertion. According to an embodiment, the present invention provides an integrated circuit. The integrated circuit includes a first port configured to be electrically coupled to a pad. The first port includes a first connection, a second connection, and a third connection. The integrated circuit also includes a first resistor having a first terminal and a second terminal. Additionally, the integrated circuit includes a second resistor having a third terminal and a forth terminal. The integrated circuit additionally includes a voltage source configured to provided a first voltage. The integrated circuit further includes a first PMOS transistor having a first gate terminal, a first drain terminal and a first source terminal. In addition, the integrated circuit includes a second PMOS transistor having a second gate terminal, a second drain terminal, and a second source terminal.

摘要翻译： 提供实时插入的系统和方法。 根据实施例，本发明提供一种集成电路。 集成电路包括被配置为电耦合到焊盘的第一端口。 第一端口包括第一连接，第二连接和第三连接。 集成电路还包括具有第一端子和第二端子的第一电阻器。 此外，集成电路包括具有第三端子和第四端子的第二电阻器。 集成电路还包括被配置为提供第一电压的电压源。 集成电路还包括具有第一栅极端子，第一漏极端子和第一源极端子的第一PMOS晶体管。 此外，集成电路包括具有第二栅极端子，第二漏极端子和第二源极端子的第二PMOS晶体管。

公开(公告)号：US20080270662A1

公开(公告)日：2008-10-30

申请号：US11780419

申请日：2007-07-19

申请人： Ta Lee Yu ,  Hai Feng Xue ,  Hui Juan Cheng

发明人： Ta Lee Yu ,  Hai Feng Xue ,  Hui Juan Cheng

IPC分类号： G06F13/00

CPC分类号： G06F13/4081

摘要： System and method for providing live insertion. According to an embodiment, the present invention provides an integrated circuit. The integrated circuit includes a first port configured to be electrically coupled to a pad. The first port includes a first connection, a second connection, and a third connection. The integrated circuit also includes a first resistor having a first terminal and a second terminal. Additionally, the integrated circuit includes a second resistor having a third terminal and a forth terminal. The integrated circuit additionally includes a voltage source configured to provided a first voltage. The integrated circuit further includes a first PMOS transistor having a first gate terminal, a first drain terminal and a first source terminal. In addition, the integrated circuit includes a second PMOS transistor having a second gate terminal, a second drain terminal, and a second source terminal.

摘要翻译： 提供实时插入的系统和方法。 根据实施例，本发明提供一种集成电路。 集成电路包括被配置为电耦合到焊盘的第一端口。 第一端口包括第一连接，第二连接和第三连接。 集成电路还包括具有第一端子和第二端子的第一电阻器。 此外，集成电路包括具有第三端子和第四端子的第二电阻器。 集成电路还包括被配置为提供第一电压的电压源。 集成电路还包括具有第一栅极端子，第一漏极端子和第一源极端子的第一PMOS晶体管。 此外，集成电路包括具有第二栅极端子，第二漏极端子和第二源极端子的第二PMOS晶体管。

公开(公告)号：US08053843B2

公开(公告)日：2011-11-08

申请号：US12483195

申请日：2009-06-11

申请人： Chi Kang Liu ,  Ta Lee Yu ,  Quan Li

发明人： Chi Kang Liu ,  Ta Lee Yu ,  Quan Li

IPC分类号： H01L27/06

CPC分类号： H01L27/0259 ,  H01L29/7835

摘要： A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage.

摘要翻译： 用于ESD保护的半导体器件包括形成在衬底内的第一导电类型的半导体衬底和第二导电类型的阱区。 井区的特征在于第一深度。 该器件包括MOS晶体管，第一双极晶体管和第二双极晶体管。 MOS晶体管包括在阱区内的第二深度的第一轻掺杂漏极（LDD）区域，以及在第一LDD区域内的漏极区域和发射极区域。 发射极区域的特征在于第二导电类型。 第一双极晶体管与发射极区域，第一LDD区域和阱区域相关联，并且其特征在于第一触发电压。 第二双极晶体管与第一LDD区，阱区和衬底相关联，并且其特征在于第二触发电压。

公开(公告)号：US08817435B2

公开(公告)日：2014-08-26

申请号：US13291093

申请日：2011-11-07

申请人： Chi Kang Liu ,  Ta Lee Yu ,  Quan Li

发明人： Chi Kang Liu ,  Ta Lee Yu ,  Quan Li

IPC分类号： H02H9/00 ,  H02H3/20 ,  H02H9/04 ,  H01L27/088 ,  H01L29/76

CPC分类号： H01L27/0259 ,  H01L29/7835

摘要： A method for making a semiconductor device includes providing a substrate of a first conductivity type and having a surface region, forming a well region of a second conductivity type and having a first depth in the substrate, adding a gate dielectric layer overlying the surface region, adding a gate layer overlying the gate dielectric layer, forming a first LDD region of the first conductivity type and having a second depth within the well region, forming an emitter region of the second conductivity type within the first LDD region, and forming a second LDD region of the first conductivity type with the well region, a channel region separates the first and second LDD regions. The method further includes forming a source region being of the first conductivity type within the second LDD region and adding an output pad coupled to both the drain and emitter regions.

摘要翻译： 一种制造半导体器件的方法包括提供第一导电类型的衬底，并具有表面区域，形成第二导电类型的阱区域并且在衬底中具有第一深度，添加覆盖在表面区域上的栅极电介质层， 添加覆盖所述栅介质层的栅极层，形成所述第一导电类型的第一LDD区，并且在所述阱区内具有第二深度，在所述第一LDD区内形成所述第二导电类型的发射极区，以及形成第二LDD 具有阱区的第一导电类型的区域，沟道区域分离第一和第二LDD区域。 该方法还包括在第二LDD区域内形成具有第一导电类型的源极区域，并且将耦合到漏极和发射极区域的输出焊盘相加。

公开(公告)号：US06642088B1

公开(公告)日：2003-11-04

申请号：US10120008

申请日：2002-04-10

申请人： Ta Lee Yu

发明人： Ta Lee Yu

IPC分类号： H01L2184

CPC分类号： H01L27/0262 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： A method to form a SCR device in the manufacture of an integrated circuit device is achieved. The method comprises providing a SOI substrate comprising a silicon layer overlying a buried oxide layer. The silicon layer further comprises a first well of a first type and a second well of a second type. A first heavily doped region of the first type is formed in the second well to form an anode terminal. A second heavily doped region of the second type is formed in the first well to form a cathode terminal and to complete the SCR device. A gate isolation method is described. A salicide method is described. LVT-SCR methods, including a floating-well, LVT-SCR method, are described.

摘要翻译： 实现了在制造集成电路器件中形成SCR器件的方法。 该方法包括提供包括覆盖在掩埋氧化物层上的硅层的SOI衬底。 硅层还包括第一类型的第一阱和第二类型的第二阱。 在第二阱中形成第一类型的第一重掺杂区以形成阳极端子。 在第一阱中形成第二类型的第二重掺杂区以形成阴极端子并完成SCR器件。 描述了栅极隔离方法。 描述了一种自杀式方法。 描述了LVT-SCR方法，包括浮阱，LVT-SCR方法。

公开(公告)号：US20120115282A1

公开(公告)日：2012-05-10

申请号：US13291093

申请日：2011-11-07

申请人： CHI KANG LIU ,  Ta Lee Yu ,  Quan Li

发明人： CHI KANG LIU ,  Ta Lee Yu ,  Quan Li

IPC分类号： H01L21/331

CPC分类号： H01L27/0259 ,  H01L29/7835

摘要： A method for making a semiconductor device includes providing a substrate of a first conductivity type and having a surface region, forming a well region of a second conductivity type and having a first depth in the substrate, adding a gate dielectric layer overlying the surface region, adding a gate layer overlying the gate dielectric layer, forming a first LDD region of the first conductivity type and having a second depth within the well region, forming an emitter region of the second conductivity type within the first LDD region, and forming a second LDD region of the first conductivity type with the well region, a channel region separates the first and second LDD regions. The method further includes forming a source region being of the first conductivity type within the second LDD region and adding an output pad coupled to both the drain and emitter regions.

摘要翻译： 一种制造半导体器件的方法包括提供第一导电类型的衬底，并具有表面区域，形成第二导电类型的阱区域并且在衬底中具有第一深度，添加覆盖在表面区域上的栅极电介质层， 添加覆盖所述栅介质层的栅极层，形成所述第一导电类型的第一LDD区，并且在所述阱区内具有第二深度，在所述第一LDD区内形成所述第二导电类型的发射极区，以及形成第二LDD 具有阱区的第一导电类型的区域，沟道区域分离第一和第二LDD区域。 该方法还包括在第二LDD区域内形成具有第一导电类型的源极区域，并且将耦合到漏极和发射极区域的输出焊盘相加。

公开(公告)号：US20100027172A1

公开(公告)日：2010-02-04

申请号：US12483195

申请日：2009-06-11

申请人： Chi Kang Liu ,  Ta Lee Yu ,  Quan Li

发明人： Chi Kang Liu ,  Ta Lee Yu ,  Quan Li

IPC分类号： H02H9/04 ,  H01L29/739 ,  H01L21/331

CPC分类号： H01L27/0259 ,  H01L29/7835

摘要： A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage.

摘要翻译： 用于ESD保护的半导体器件包括形成在衬底内的第一导电类型的半导体衬底和第二导电类型的阱区。 井区的特征在于第一深度。 该器件包括MOS晶体管，第一双极晶体管和第二双极晶体管。 MOS晶体管包括在阱区内的第二深度的第一轻掺杂漏极（LDD）区域，以及在第一LDD区域内的漏极区域和发射极区域。 发射极区域的特征在于第二导电类型。 第一双极晶体管与发射极区域，第一LDD区域和阱区域相关联，并且其特征在于第一触发电压。 第二双极晶体管与第一LDD区，阱区和衬底相关联，并且其特征在于第二触发电压。

公开(公告)号：US08368186B2

公开(公告)日：2013-02-05

申请号：US13076269

申请日：2011-03-30

申请人： Ta Lee Yu ,  Chi Kang Liu ,  Jing Liu

发明人： Ta Lee Yu ,  Chi Kang Liu ,  Jing Liu

IPC分类号： H01L23/552

CPC分类号： H01L27/0255 ,  H01L24/05 ,  H01L2924/12036 ,  H01L2924/13034 ,  H01L2924/14 ,  H01L2924/00

摘要： An ESD device includes a first and second well regions disposed in a semiconductor substrate. The first well region comprises a plurality of N wells spaced at a predetermined length. A heavily doped P+ region and a heavily doped N+ region are disposed in each of the N wells. The heavily doped N+ region is coupled to Vdd and a heavily doped P+ region in an N well is electrically coupled to the heavily doped N+ region in an adjacent N well. The second well region comprises a P well abutting an N well. A heavily doped P+ region and a heavily doped N+ region are disposed in the P well. The heavily doped N+ region in the P well is electrically coupled to the heavily doped P+ region of the adjacent N well in common with an I/O circuit, and the heavily doped P+ region is coupled to Vss.

摘要翻译： ESD器件包括设置在半导体衬底中的第一和第二阱区。 第一阱区域包括以预定长度间隔开的多个N阱。 重掺杂的P +区域和重掺杂的N +区域设置在每个N个阱中。 重掺杂N +区域耦合到Vdd，并且N阱中的重掺杂P +区域电耦合到相邻N阱中的重掺杂N +区域。 第二井区域包括邻接N井的P井。 在P阱中设置重掺杂P +区和重掺杂N +区。 P阱中的重掺杂N +区域与I / O电路共同地电耦合到相邻N阱的重掺杂P +区域，并且重掺杂P +区域耦合到Vss。

公开(公告)号：US20120074539A1

公开(公告)日：2012-03-29

申请号：US13076269

申请日：2011-03-30

申请人： Ta Lee Yu ,  Chi Kang Liu ,  Jing Liu

发明人： Ta Lee Yu ,  Chi Kang Liu ,  Jing Liu

IPC分类号： H01L23/552

CPC分类号： H01L27/0255 ,  H01L24/05 ,  H01L2924/12036 ,  H01L2924/13034 ,  H01L2924/14 ,  H01L2924/00

摘要： An ESD device includes a first and second well regions disposed in a semiconductor substrate. The first well region comprises a plurality of N wells spaced at a predetermined length. A heavily doped P+ region and a heavily doped N+ region are disposed in each of the N wells. The heavily doped N+ region is coupled to Vdd and a heavily doped P+ region in an N well is electrically coupled to the heavily doped N+ region in an adjacent N well. The second well region comprises a P well abutting an N well. A heavily doped P+ region and a heavily doped N+ region are disposed in the P well. The heavily doped N+ region in the P well is electrically coupled to the heavily doped P+ region of the adjacent N well in common with an I/O circuit, and the heavily doped P+ region is coupled to Vss.

摘要翻译： ESD器件包括设置在半导体衬底中的第一和第二阱区。 第一阱区域包括以预定长度间隔开的多个N阱。 重掺杂的P +区域和重掺杂的N +区域设置在每个N个阱中。 重掺杂N +区域耦合到Vdd，并且N阱中的重掺杂P +区域电耦合到相邻N阱中的重掺杂N +区域。 第二井区域包括邻接N井的P井。 在P阱中设置重掺杂P +区和重掺杂N +区。 P阱中的重掺杂N +区域与I / O电路共同地电耦合到相邻N阱的重掺杂P +区域，并且重掺杂P +区域耦合到Vss。

公开(公告)号：US06507087B1

公开(公告)日：2003-01-14

申请号：US10188592

申请日：2002-07-03

申请人： Ta Lee Yu

发明人： Ta Lee Yu

IPC分类号： H01L2900

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fusible link device and a method of making same. The fusible link device comprising a poly layer having a center undoped portion and two doped end portions. The center undoped portion having a first resistance and the two doped end portions each having a second resistance that is lower than the first resistance. A silicide layer is formed over the poly layer with the silicide layer having a third resistance lower than the second resistance. The silicide layer agglomerating to form an electrical discontinuity within a discontinuity area in response to a predetermined programming potential being applied across the silicide layer, such that the resistance of the fusible link device can be selectively increased. The agglomeration of the silicide layer occurring over the center undoped portion of the poly layer. Contacts are electrically coupled to the two doped poly layer end portions for receiving the programming potential.