公开(公告)号：US08817435B2

公开(公告)日：2014-08-26

申请号：US13291093

申请日：2011-11-07

申请人： Chi Kang Liu ,  Ta Lee Yu ,  Quan Li

发明人： Chi Kang Liu ,  Ta Lee Yu ,  Quan Li

IPC分类号： H02H9/00 ,  H02H3/20 ,  H02H9/04 ,  H01L27/088 ,  H01L29/76

CPC分类号： H01L27/0259 ,  H01L29/7835

摘要： A method for making a semiconductor device includes providing a substrate of a first conductivity type and having a surface region, forming a well region of a second conductivity type and having a first depth in the substrate, adding a gate dielectric layer overlying the surface region, adding a gate layer overlying the gate dielectric layer, forming a first LDD region of the first conductivity type and having a second depth within the well region, forming an emitter region of the second conductivity type within the first LDD region, and forming a second LDD region of the first conductivity type with the well region, a channel region separates the first and second LDD regions. The method further includes forming a source region being of the first conductivity type within the second LDD region and adding an output pad coupled to both the drain and emitter regions.

摘要翻译： 一种制造半导体器件的方法包括提供第一导电类型的衬底，并具有表面区域，形成第二导电类型的阱区域并且在衬底中具有第一深度，添加覆盖在表面区域上的栅极电介质层， 添加覆盖所述栅介质层的栅极层，形成所述第一导电类型的第一LDD区，并且在所述阱区内具有第二深度，在所述第一LDD区内形成所述第二导电类型的发射极区，以及形成第二LDD 具有阱区的第一导电类型的区域，沟道区域分离第一和第二LDD区域。 该方法还包括在第二LDD区域内形成具有第一导电类型的源极区域，并且将耦合到漏极和发射极区域的输出焊盘相加。

公开(公告)号：US20110080381A1

公开(公告)日：2011-04-07

申请号：US12844413

申请日：2010-07-27

申请人： Huimin Tsai ,  Chi Kang Liu

发明人： Huimin Tsai ,  Chi Kang Liu

IPC分类号： G06F3/038 ,  H03J7/04

CPC分类号： H03J1/0008 ,  G06F1/08 ,  G09G2320/0693 ,  H03J7/04 ,  H03L7/06

摘要： A portable control apparatus includes a driver, a baseband controller, and a crystal oscillator. The driver includes an oscillating circuit that generates a feedback signal. The baseband controller coupled to the driver receives the feedback signal, and outputs a calibrating signal to the driver according to the feedback signal. The crystal oscillator coupled to the baseband controller generates an accurate output frequency for operating the baseband controller.

摘要翻译： 便携式控制装置包括驱动器，基带控制器和晶体振荡器。 驱动器包括产生反馈信号的振荡电路。 耦合到驱动器的基带控制器接收反馈信号，并根据反馈信号向驱动器输出校准信号。 耦合到基带控制器的晶体振荡器产生用于操作基带控制器的精确输出频率。

公开(公告)号：US20110037177A1

公开(公告)日：2011-02-17

申请号：US12582690

申请日：2009-10-20

申请人： CHI KANG LIU ,  TALEE YU

发明人： CHI KANG LIU ,  TALEE YU

IPC分类号： H01L23/488

CPC分类号： H01L24/05 ,  H01L23/522 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01204 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

摘要： An integrated circuit device comprising an improved bonding pad structure. The device has a semiconductor substrate. A plurality of active MOS devices are formed on the semiconductor substrate. The device has an interlayer dielectric layer overlying the plurality of active MOS devices and at least one single metal bonding pad formed on the interlayer dielectric layer and directly over at least one of the active devices. At least four edge regions are formed on a square shape of the at least one single metal bonding pad. An angled cut region is formed on each of the four edge regions. Preferably, the angled cut region is within a periphery of the square shape of the at least one single metal bonding pad. A passivation layer having an opening is formed over the at least single metal bonding pad. The device has a buffer metal layer free region between the plurality of active MOS devices and the at least one single metal bonding pad. The buffer metal layer free region is within an entirety of the interlayer dielectric layer. The passivation is substantially free from the buffer metal layer underlying the single metal bonding pad.

摘要翻译： 一种集成电路器件，包括改进的焊盘结构。 该器件具有半导体衬底。 在半导体衬底上形成多个有源MOS器件。 该器件具有覆盖多个有源MOS器件的层间介质层和形成在层间介质层上并直接位于至少一个有源器件上的至少一个单一金属焊盘。 至少四个边缘区域形成在至少一个单个金属接合焊盘的正方形上。 在四个边缘区域中的每一个上形成有角度切割区域。 优选地，成角度切割区域在至少一个单个金属粘合垫的正方形的周边内。 在至少单个金属焊盘上方形成具有开口的钝化层。 该器件在多个有源MOS器件与至少一个单一金属焊盘之间具有缓冲金属层自由区。 缓冲金属层自由区在层间电介质层的整体内。 钝化基本上不含有单个金属焊盘下面的缓冲金属层。

公开(公告)号：US20100277458A1

公开(公告)日：2010-11-04

申请号：US12769901

申请日：2010-04-29

申请人： Chi Kang Liu ,  Chin-Wei Lin ,  Min-Nan Hsieh

发明人： Chi Kang Liu ,  Chin-Wei Lin ,  Min-Nan Hsieh

IPC分类号： G06F3/038

CPC分类号： G09G3/3688 ,  G09G2330/06

摘要： A driving circuit on a liquid crystal display (LCD) panel and associated control method is provided. The LCD panel connected to a display control circuit via a flexible print circuit (FPC) includes a master source driver, for outputting a digital image signal in compliance with a first electrical specification via an FPC board and converting the digital image signal to a gate driving signal and a slave source driving signal, which are in compliance with a second electrical specification; a gate driver, for receiving the gate driving signal in compliance with the second electrical specification; and a slave source driver, for receiving the slave source driving signal in compliance with the second electrical specification. The master source driver, the slave source driver and the gate driver drive a thin-film transistor (TFT) on the LCD panel.

摘要翻译： 提供了液晶显示器（LCD）面板上的驱动电路和相关的控制方法。 通过柔性印刷电路（FPC）连接到显示控制电路的LCD面板包括主源驱动器，用于经由FPC板输出符合第一电气规范的数字图像信号，并将数字图像信号转换为门驱动 信号和从源驱动信号，其符合第二电气规范; 门驱动器，用于接收符合第二电气规范的门驱动信号; 和从源驱动器，用于接收符合第二电气规范的从源驱动信号。 主源驱动器，从源驱动器和栅极驱动器驱动LCD面板上的薄膜晶体管（TFT）。

公开(公告)号：US07265422B2

公开(公告)日：2007-09-04

申请号：US11215492

申请日：2005-08-29

申请人： Talee Yu ,  Chi Kang Liu

发明人： Talee Yu ,  Chi Kang Liu

IPC分类号： H01L23/62

CPC分类号： H01L27/0259

摘要： Techniques for ESD protection are provided. An ESD protection device includes a first well region and a second well region disposed in a semiconductor substrate, with an isolation region therebetween. N+ implant regions are disposed in the second well region and are coupled in common at a first node. NLDD regions are disposed between the N+ implant regions, and pocket implants underlie each of the NLDD regions. Current discharge paths are defined by corresponding NLDD regions and pocket implants when a voltage of the first node exceeds a breakdown voltage. In a specific embodiment, the breakdown voltage is less than a breakdown voltage for a logic gate oxide.

摘要翻译： 提供ESD保护技术。 ESD保护装置包括设置在半导体衬底中的第一阱区和第二阱区，其间具有隔离区。 N +注入区域设置在第二阱区域中并且在第一节点处共同耦合。 NLDD区域设置在N +植入区域之间，并且口袋植入物构成每个NLDD区域的基础。 当第一节点的电压超过击穿电压时，当前的放电路径由相应的NLDD区域和口袋植入物限定。 在具体实施例中，击穿电压小于逻辑栅极氧化物的击穿电压。

公开(公告)号：US06559018B1

公开(公告)日：2003-05-06

申请号：US10053308

申请日：2002-01-18

申请人： Chi-Kang Liu ,  Tien-Chi Ke ,  Hsin-Li Cheng

发明人： Chi-Kang Liu ,  Tien-Chi Ke ,  Hsin-Li Cheng

IPC分类号： H01L21425

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L29/665

摘要： A new processing sequence is provided for the process of creating salicided layers of CoSix. A conventional gate electrode is formed up to the point where the process of salicidation has to be performed. At that time a layer of cobalt is deposited over the surface of the gate electrode, a first anneal is applied to the deposited layer of cobalt. The layer of cobalt is then selectively etched to formed the contact surfaces of the gate electrode after which, significantly and as a major deviation from previous methods of creating a salicided layer of CoSix, silicon is implanted into the surface of the created layer of CoSix. This silicon implant relieves a silicon deficiency into the first annealed layer of CoSix, this silicon deficiency has experimentally been determined as being the essential cause for the occurrence of Co—Si agglomeration after a second thermal anneal. After the silicon implantation has been completed, a second thermal anneal is applied to the created layer of CoSix. The occurrence of Co—Si agglomeration is in this manner essentially eliminated.

摘要翻译： 提供了一个新的处理顺序，用于创建CoSix的水浸层的过程。 形成常规的栅电极，直至必须进行盐化过程。 此时，在栅电极的表面上沉积钴层，首先对钴沉积层进行退火。 然后选择性地蚀刻钴层以形成栅电极的接触表面，之后，与先前创建CoSix的水杨酸层的方法相比，显着地和作为主要偏离，硅被植入到所产生的CoSix层的表面中。 这种硅植入物将硅缺陷释放到CoSix的第一退火层中，这种硅缺陷已经被确定为在第二热退火之后发生Co-Si聚集的重要原因。 在硅注入完成之后，将第二次热退火应用于所创建的CoSix层。 以这种方式基本上消除了Co-Si团聚的发生。

公开(公告)号：US06468915B1

公开(公告)日：2002-10-22

申请号：US09666317

申请日：2000-09-21

申请人： Chi-Kang Liu

发明人： Chi-Kang Liu

IPC分类号： H01L21302

CPC分类号： H01L29/6659 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02274 ,  H01L21/0276 ,  H01L21/28247 ,  H01L21/31111 ,  H01L21/31662 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656

摘要： A method is taught for removing a silicon oxynitride ARC from over a polysilicon gate after the gate is patterned. The ARC is removed by wet etching without damaging or undercutting the polysilicon gate. This is accomplished by protecting the lateral sides of a polysilicon gate with a thin silicon oxide layer prior to the performing the wet etch. The method is primarily directed towards removal of a silicon oxynitride ARC layer from the upper surface of the polysilicon gate electrode in a salicide process, although a silicon nitride layer may also be removed by the same method. The protective silicon oxide is formed by rapid thermal oxidation in O2 or by plasma oxidation in O2 and H2O. After oxidation, the ARC is removed with hot H3PO4. The protective silicon oxide protects the lateral surfaces of the polysilicon gate from attack by the acid. Following implantation of LDD regions, a conformal sidewall layer is deposited and the sidewalls formed in the conventional manner. When oxide/nitride sidewalls are formed, the protective oxide serves as a pad layer under the nitride. The method is particularly effective in preventing stress induced cracks in a composite oxide/nitride sidewall which has a foot. Elimination of gate undercutting by gate edge protection, according to the method described, eliminates excessive sidewall thickness in the vicinity of the corner at the foot and thereby minimizes stress in this region.

摘要翻译： 在栅极被图案化之后，教导了从多晶硅栅极上去除氮氧化硅ARC的方法。 通过湿蚀刻去除ARC，而不会损坏或削弱多晶硅栅极。 这是通过在执行湿蚀刻之前用薄氧化硅层保护多晶硅栅极的侧面来实现的。 该方法主要是针对在硅化物工艺中从多晶硅栅电极的上表面去除氮氧化硅ARC层，尽管也可以通过相同的方法去除氮化硅层。 保护性氧化硅通过O2中的快速热氧化或通过在O 2和H 2 O中的等离子体氧化形成。 氧化后，用热的H3PO4除去ARC。 保护性氧化硅保护多晶硅栅极的侧表面免受酸的侵蚀。 在LDD区域的注入之后，沉积保形侧壁层，并以常规方式形成侧壁。 当形成氧化物/氮化物侧壁时，保护氧化物用作氮化物之下的焊盘层。 该方法在防止具有脚的复合氧化物/氮化物侧壁中的应力诱发裂纹方面特别有效。 根据所述的方法，通过栅极边缘保护消除栅极底切消除了脚处拐角附近的过多侧壁厚度，从而使该区域的应力最小化。

公开(公告)号：US06350390B1

公开(公告)日：2002-02-26

申请号：US09507808

申请日：2000-02-22

申请人： Chi Kang Liu ,  Chang Jen Shieh ,  Pei Hung Chen

发明人： Chi Kang Liu ,  Chang Jen Shieh ,  Pei Hung Chen

IPC分类号： G05D500

CPC分类号： G05D5/03 ,  H01L21/31144 ,  H01L21/32139

摘要： A feed forward method for forming within a microelectronic fabrication a patterned target layer with controlled critical dimension (CD) first provides a substrate having formed thereover a blanket target layer, in turn having formed thereover a blanket anti-reflective coating (ARC) layer, in turn having formed thereover a paltered photoresist layer. There is then established a correlation which describes an interrelation between the patterned photoresist layer linewidth and a plasma species concentration within a plasma for forming from the blanket anti-reflective coating (ARC) layer a patterned anti-reflective coating (ARC) layer such that a patterned target layer subsequently formed from the blanket target layer is formed with a patterned target layer measured linewidth closer to a patterned target layer target linewidth The linewidth of the patterned photoresist layer is then measured and there is determined a deviation of the patterned photoresist measured linewidth from a patterned photoresist layer target linewidth. The plasma species concentration is then adjusted when etching the blanket anti-reflective coating (ARC) layer to form the patterned anti-reflective coating (ARC) layer such that the patterned target layer may be formed with the patterned target layer measured linewidth closer to a patterned target layer target linewidth.

摘要翻译： 用于在微电子制造中形成具有受控临界尺寸（CD）的图案化目标层的前馈方法首先提供了在其上形成有覆盖目标层的基底，其又形成在覆盖层抗反射涂层（ARC）层上， 在其上形成有改变的光致抗蚀剂层。 然后建立描述图案化光致抗蚀剂层线宽和等离子体中等离子体物质浓度之间的相互关系的相关性，以从毯状抗反射涂层（ARC）层形成图案化抗反射涂层（ARC）层，使得 随后由覆盖目标层形成的图案化目标层形成有图案化目标层，测量的线宽更接近图案化目标层目标线宽图案化光致抗蚀剂层的线宽然后被测量，并且确定图案化的光致抗蚀剂测量的线宽与 图案化的光刻胶层目标线宽。 然后在蚀刻毯子抗反射涂层（ARC）层时调整等离子体物质浓度，以形成图案化抗反射涂层（ARC）层，使得图案化目标层可以形成有图案化目标层，测量的线宽更接近于 图案目标层目标线宽。

公开(公告)号：US06265257B1

公开(公告)日：2001-07-24

申请号：US09409877

申请日：1999-10-01

申请人： Woan Jen Hsu ,  Chi Kang Liu

发明人： Woan Jen Hsu ,  Chi Kang Liu

IPC分类号： H01L218238

CPC分类号： H01L21/76849 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an antifuse interconnect structure, for a one-time fusible link, to be used with field-programmable gate arrays, has been developed. The process features the use of an amorphous silicon layer, used as the antifuse layer, with the amorphous silicon layer protected by a thin barrier layer, during the patterning procedure. The protected antifuse layer results in a reproducible thickness, and thus reproducible pulsing voltages, needed for rupturing of the antifuse layer. Planarization of an underlying metal plug, via a conductor layer refill procedure, offers a smooth top surface, flush with the top surface of the adjacent interlevel dielectric layer, for the overlying antifuse layer.

摘要翻译： 已经开发了用于与现场可编程门阵列一起使用的用于一次性可熔链路的反熔丝互连结构的方法。 该工艺的特征在于在图案化步骤期间使用非晶硅层作为反熔丝层，非晶硅层被薄的阻挡层保护。 受保护的反熔丝层导致反熔丝层破裂所需的可再现厚度，并因此产生可再现的脉冲电压。 通过导体层再填充程序对底层金属插头进行平面化，提供与相邻层间电介质层的顶表面齐平的平滑顶表面，用于覆盖反熔丝层。

公开(公告)号：US6057230A

公开(公告)日：2000-05-02

申请号：US156051

申请日：1998-09-17

申请人： Chi Kang Liu

发明人： Chi Kang Liu

IPC分类号： H01L21/3213 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/32136 ,  H01L21/76838

摘要： A method for fabricating a copper, or a copper-titanium nitride-titanium, interconnect structure, using a low temperature RIE patterning procedure, has been developed. The RIE patterning procedure features the use of SiCl.sub.4 and nitrogen, as reactants, with amount of nitrogen supplied, being equal to, or greater than, the SiCl.sub.4 level. The addition of nitrogen, to the etching ambient, results in the formation of a non-cross-linked, by-product, which is easily removed during the patterning procedure, this not interfering with the creation of interconnect structure. Without the addition of nitrogen, a cross-linked, by-product, would be formed, during the low temperature RIE procedure, with the redeposited, cross-linked, by-product, interfering with the patterning of the copper interconnect structure.

摘要翻译： 已经开发了使用低温RIE图案化方法制造铜或铜 - 氮化钛 - 钛互连结构的方法。 RIE图案化程序的特征在于使用SiCl 4和氮作为反应物，其供应的氮量等于或大于SiCl 4水平。 在蚀刻环境中添加氮导致形成非交联的副产物，其在图案化过程中容易除去，这不妨碍互连结构的产生。 在不加氮气的情况下，在低温RIE工艺期间，会形成交联的副产物，其中再沉积的交联副产物妨碍铜互连结构的图案化。