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    Device and methods for electrostatic discharge protection
    1.
    发明授权
    Device and methods for electrostatic discharge protection 有权
    静电放电保护装置及方法

    公开(公告)号：US08368186B2

    公开(公告)日：2013-02-05

    申请号：US13076269

    申请日：2011-03-30

    申请人： Ta Lee Yu ,  Chi Kang Liu ,  Jing Liu

    发明人： Ta Lee Yu ,  Chi Kang Liu ,  Jing Liu

    IPC分类号： H01L23/552

    CPC分类号： H01L27/0255 ,  H01L24/05 ,  H01L2924/12036 ,  H01L2924/13034 ,  H01L2924/14 ,  H01L2924/00

    摘要： An ESD device includes a first and second well regions disposed in a semiconductor substrate. The first well region comprises a plurality of N wells spaced at a predetermined length. A heavily doped P+ region and a heavily doped N+ region are disposed in each of the N wells. The heavily doped N+ region is coupled to Vdd and a heavily doped P+ region in an N well is electrically coupled to the heavily doped N+ region in an adjacent N well. The second well region comprises a P well abutting an N well. A heavily doped P+ region and a heavily doped N+ region are disposed in the P well. The heavily doped N+ region in the P well is electrically coupled to the heavily doped P+ region of the adjacent N well in common with an I/O circuit, and the heavily doped P+ region is coupled to Vss.

    摘要翻译： ESD器件包括设置在半导体衬底中的第一和第二阱区。 第一阱区域包括以预定长度间隔开的多个N阱。 重掺杂的P +区域和重掺杂的N +区域设置在每个N个阱中。 重掺杂N +区域耦合到Vdd，并且N阱中的重掺杂P +区域电耦合到相邻N阱中的重掺杂N +区域。 第二井区域包括邻接N井的P井。 在P阱中设置重掺杂P +区和重掺杂N +区。 P阱中的重掺杂N +区域与I / O电路共同地电耦合到相邻N阱的重掺杂P +区域，并且重掺杂P +区域耦合到Vss。

    DEVICE AND METHODS FOR ELECTROSTATIC DISCHARGE PROTECTION
    2.
    发明申请
    DEVICE AND METHODS FOR ELECTROSTATIC DISCHARGE PROTECTION 有权
    静电放电保护装置及方法

    公开(公告)号：US20120074539A1

    公开(公告)日：2012-03-29

    申请号：US13076269

    申请日：2011-03-30

    申请人： Ta Lee Yu ,  Chi Kang Liu ,  Jing Liu

    发明人： Ta Lee Yu ,  Chi Kang Liu ,  Jing Liu

    IPC分类号： H01L23/552

    CPC分类号： H01L27/0255 ,  H01L24/05 ,  H01L2924/12036 ,  H01L2924/13034 ,  H01L2924/14 ,  H01L2924/00

    摘要： An ESD device includes a first and second well regions disposed in a semiconductor substrate. The first well region comprises a plurality of N wells spaced at a predetermined length. A heavily doped P+ region and a heavily doped N+ region are disposed in each of the N wells. The heavily doped N+ region is coupled to Vdd and a heavily doped P+ region in an N well is electrically coupled to the heavily doped N+ region in an adjacent N well. The second well region comprises a P well abutting an N well. A heavily doped P+ region and a heavily doped N+ region are disposed in the P well. The heavily doped N+ region in the P well is electrically coupled to the heavily doped P+ region of the adjacent N well in common with an I/O circuit, and the heavily doped P+ region is coupled to Vss.

    摘要翻译： ESD器件包括设置在半导体衬底中的第一和第二阱区。 第一阱区域包括以预定长度间隔开的多个N阱。 重掺杂的P +区域和重掺杂的N +区域设置在每个N个阱中。 重掺杂N +区域耦合到Vdd，并且N阱中的重掺杂P +区域电耦合到相邻N阱中的重掺杂N +区域。 第二井区域包括邻接N井的P井。 在P阱中设置重掺杂P +区和重掺杂N +区。 P阱中的重掺杂N +区域与I / O电路共同地电耦合到相邻N阱的重掺杂P +区域，并且重掺杂P +区域耦合到Vss。

    INTEGRATED ELECTROSTATIC DISCHARGE (ESD) DEVICE
    3.
    发明申请
    INTEGRATED ELECTROSTATIC DISCHARGE (ESD) DEVICE 有权
    集成静电放电（ESD）器件

    公开(公告)号：US20100027172A1

    公开(公告)日：2010-02-04

    申请号：US12483195

    申请日：2009-06-11

    申请人： Chi Kang Liu ,  Ta Lee Yu ,  Quan Li

    发明人： Chi Kang Liu ,  Ta Lee Yu ,  Quan Li

    IPC分类号： H02H9/04 ,  H01L29/739 ,  H01L21/331

    CPC分类号： H01L27/0259 ,  H01L29/7835

    摘要： A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage.

    摘要翻译： 用于ESD保护的半导体器件包括形成在衬底内的第一导电类型的半导体衬底和第二导电类型的阱区。 井区的特征在于第一深度。 该器件包括MOS晶体管，第一双极晶体管和第二双极晶体管。 MOS晶体管包括在阱区内的第二深度的第一轻掺杂漏极（LDD）区域，以及在第一LDD区域内的漏极区域和发射极区域。 发射极区域的特征在于第二导电类型。 第一双极晶体管与发射极区域，第一LDD区域和阱区域相关联，并且其特征在于第一触发电压。 第二双极晶体管与第一LDD区，阱区和衬底相关联，并且其特征在于第二触发电压。

    Integrated electrostatic discharge (ESD) device
    4.
    发明授权
    Integrated electrostatic discharge (ESD) device 有权
    集成静电放电（ESD）器件

    公开(公告)号：US08891213B2

    公开(公告)日：2014-11-18

    申请号：US13244292

    申请日：2011-09-24

    申请人： Chi Kang Liu ,  Ta Lee Yu ,  Quan Li

    发明人： Chi Kang Liu ,  Ta Lee Yu ,  Quan Li

    IPC分类号： H02H9/00 ,  H01L27/02 ,  H01L29/78 ,  H02H3/22 ,  H02H3/02 ,  H02H3/08

    CPC分类号： H01L27/0259 ,  H01L29/7835

    摘要： A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage.

    摘要翻译： 用于ESD保护的半导体器件包括形成在衬底内的第一导电类型的半导体衬底和第二导电类型的阱区。 井区的特征在于第一深度。 该器件包括MOS晶体管，第一双极晶体管和第二双极晶体管。 MOS晶体管包括在阱区内的第二深度的第一轻掺杂漏极（LDD）区域，以及在第一LDD区域内的漏极区域和发射极区域。 发射极区域的特征在于第二导电类型。 第一双极晶体管与发射极区域，第一LDD区域和阱区域相关联，并且其特征在于第一触发电压。 第二双极晶体管与第一LDD区，阱区和衬底相关联，并且其特征在于第二触发电压。

    INTEGRATED ELECTROSTATIC DISCHARGE (ESD) DEVICE
    5.
    发明申请
    INTEGRATED ELECTROSTATIC DISCHARGE (ESD) DEVICE 有权
    集成静电放电（ESD）器件

    公开(公告)号：US20120014021A1

    公开(公告)日：2012-01-19

    申请号：US13244292

    申请日：2011-09-24

    申请人： Chi Kang Liu ,  TA Lee Yu ,  Quan Li

    发明人： Chi Kang Liu ,  TA Lee Yu ,  Quan Li

    IPC分类号： H02H9/04 ,  H01L21/332

    CPC分类号： H01L27/0259 ,  H01L29/7835

    摘要： A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage.

    摘要翻译： 用于ESD保护的半导体器件包括形成在衬底内的第一导电类型的半导体衬底和第二导电类型的阱区。 井区的特征在于第一深度。 该器件包括MOS晶体管，第一双极晶体管和第二双极晶体管。 MOS晶体管包括在阱区内的第二深度的第一轻掺杂漏极（LDD）区域，以及在第一LDD区域内的漏极区域和发射极区域。 发射极区域的特征在于第二导电类型。 第一双极晶体管与发射极区域，第一LDD区域和阱区域相关联，并且其特征在于第一触发电压。 第二双极晶体管与第一LDD区，阱区和衬底相关联，并且其特征在于第二触发电压。

    Integrated electrostatic discharge (ESD) device
    6.
    发明授权
    Integrated electrostatic discharge (ESD) device 有权
    集成静电放电（ESD）器件

    公开(公告)号：US08053843B2

    公开(公告)日：2011-11-08

    申请号：US12483195

    申请日：2009-06-11

    申请人： Chi Kang Liu ,  Ta Lee Yu ,  Quan Li

    发明人： Chi Kang Liu ,  Ta Lee Yu ,  Quan Li

    IPC分类号： H01L27/06

    CPC分类号： H01L27/0259 ,  H01L29/7835

    摘要： A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage.

    摘要翻译： 用于ESD保护的半导体器件包括形成在衬底内的第一导电类型的半导体衬底和第二导电类型的阱区。 井区的特征在于第一深度。 该器件包括MOS晶体管，第一双极晶体管和第二双极晶体管。 MOS晶体管包括在阱区内的第二深度的第一轻掺杂漏极（LDD）区域，以及在第一LDD区域内的漏极区域和发射极区域。 发射极区域的特征在于第二导电类型。 第一双极晶体管与发射极区域，第一LDD区域和阱区域相关联，并且其特征在于第一触发电压。 第二双极晶体管与第一LDD区，阱区和衬底相关联，并且其特征在于第二触发电压。

    Integrated electrostatic discharge (ESD) device
    7.
    发明授权
    Integrated electrostatic discharge (ESD) device 有权
    集成静电放电（ESD）器件

    公开(公告)号：US08817435B2

    公开(公告)日：2014-08-26

    申请号：US13291093

    申请日：2011-11-07

    申请人： Chi Kang Liu ,  Ta Lee Yu ,  Quan Li

    发明人： Chi Kang Liu ,  Ta Lee Yu ,  Quan Li

    IPC分类号： H02H9/00 ,  H02H3/20 ,  H02H9/04 ,  H01L27/088 ,  H01L29/76

    CPC分类号： H01L27/0259 ,  H01L29/7835

    摘要： A method for making a semiconductor device includes providing a substrate of a first conductivity type and having a surface region, forming a well region of a second conductivity type and having a first depth in the substrate, adding a gate dielectric layer overlying the surface region, adding a gate layer overlying the gate dielectric layer, forming a first LDD region of the first conductivity type and having a second depth within the well region, forming an emitter region of the second conductivity type within the first LDD region, and forming a second LDD region of the first conductivity type with the well region, a channel region separates the first and second LDD regions. The method further includes forming a source region being of the first conductivity type within the second LDD region and adding an output pad coupled to both the drain and emitter regions.

    摘要翻译： 一种制造半导体器件的方法包括提供第一导电类型的衬底，并具有表面区域，形成第二导电类型的阱区域并且在衬底中具有第一深度，添加覆盖在表面区域上的栅极电介质层， 添加覆盖所述栅介质层的栅极层，形成所述第一导电类型的第一LDD区，并且在所述阱区内具有第二深度，在所述第一LDD区内形成所述第二导电类型的发射极区，以及形成第二LDD 具有阱区的第一导电类型的区域，沟道区域分离第一和第二LDD区域。 该方法还包括在第二LDD区域内形成具有第一导电类型的源极区域，并且将耦合到漏极和发射极区域的输出焊盘相加。

    E-Fuse and Associated Control Circuit
    9.
    发明申请
    E-Fuse and Associated Control Circuit 有权
    电子保险丝及相关控制电路

    公开(公告)号：US20100213551A1

    公开(公告)日：2010-08-26

    申请号：US12702984

    申请日：2010-02-09

    申请人： Chi Kang Liu ,  Chin-Wei Lin ,  Min-Nan Hsieh

    发明人： Chi Kang Liu ,  Chin-Wei Lin ,  Min-Nan Hsieh

    IPC分类号： H01L27/105 ,  H01L23/525

    CPC分类号： H01L27/0629 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An e-fuse and an e-fuse control circuit are provided. The e-fuse includes a polysilicon layer and a metal silicide layer stacked on the polysilicon layer. The e-fuse operates in an open state when the silicide layer is broken by burning while one portion of the polysilicon layer is exposed.

    摘要翻译： 提供电子熔丝和电熔丝控制电路。 电熔丝包括堆叠在多晶硅层上的多晶硅层和金属硅化物层。 当硅化物层通过燃烧而破坏时，e熔丝工作在打开状态，同时暴露多晶硅层的一部分。