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公开(公告)号：US20060004528A1
公开(公告)日：2006-01-05
申请号：US11090275
申请日：2005-03-28
CPC分类号： G06F8/71
摘要： In a similar source-code extracting apparatus, a comparison-source source-code fragment specifying unit accepts specification of a source-code fragment that is specified as a reference for comparison, a comparison-target source-code specifying unit accepts specification of a source code group and extracts a source-code fragment similar to the source-code fragment from the source code group, and a result output unit outputs the result of extraction. A comparison-target source-code fragment extracting unit extracts the source code to be compared for similarity with the comparison-source source-code fragment from the source code group, by referring to a syntax tree created from the comparison-source source-code fragment and a syntax tree created from the source code group. Also, a similar source-code extracting method and a computer readable recording medium in which a similar source-code extraction program for extracting a similar source-code fragment from a source code described in a predetermined programming language is recorded are disclosed.
摘要翻译： 在类似的源代码提取装置中，比较源代码片段指定单元接受指定为比较的参考的源代码片段的指定，比较目标源代码指定单元接受源的指定 代码组，并从源代码组中提取类似于源代码片段的源代码片段，结果输出单元输出提取结果。 比较目标源代码片段提取单元通过参考从比较源代码片段创建的语法树来提取与源代码组的比较源代码片段进行比较的相似性源代码 以及从源代码组创建的语法树。 此外，公开了一种类似的源代码提取方法和计算机可读记录介质，其中记录了用于从以预定编程语言描述的源代码提取类似的源代码片段的类似的源代码提取程序。
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公开(公告)号：US20090058695A1
公开(公告)日：2009-03-05
申请号：US12197133
申请日：2008-08-22
申请人： Yiliang Bao , Toshiaki Yoshino , Kai Wang
发明人： Yiliang Bao , Toshiaki Yoshino , Kai Wang
摘要： Techniques for optimizing the Context-based Adaptive Binary Arithmetic Coding (CABAC) bitstream decoding are disclosed. In one configuration, a device has a first processing circuit operative to decode a Context-based Adaptive Binary Arithmetic Coding (CABAC) bitstream into an intermediate signal having a CABAC decoded standard format and a decoded order. A second processing circuit decodes the intermediate signal using a non-CABAC decoding standard. A buffer is provided between the first and second processing circuits to improve processing speeds.
摘要翻译： 公开了用于优化基于上下文的自适应二进制算术编码（CABAC）比特流解码的技术。 在一种配置中，设备具有操作以将基于上下文的自适应二进制算术编码（CABAC）比特流解码为具有CABAC解码标准格式和解码顺序的中间信号的第一处理电路。 第二处理电路使用非CABAC解码标准解码中间信号。 在第一和第二处理电路之间提供缓冲器以提高处理速度。
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公开(公告)号：US5644518A
公开(公告)日：1997-07-01
申请号：US622051
申请日：1996-03-26
摘要： An nth degree function computing device having a low-cost, small scale circuit in which no multipliers are present and which allows high-speed computing operations. The nth degree function computing device comprises two series operators 32 and 38 connected in series, with an adder 44 inserted between them, and with an adder 48 inserted between the output terminal of the second-stage series operator 38 and device output terminal 46. A constant 2a.sub.2 is sent from constant generator 50 to the first input terminal of an adder 34 of the first-stage series operator 32. A constant (a.sub.1 -a.sub.2) is sent from constant generator 52 to first input terminal of adder 44. A constant a.sub.0 is sent from constant generator 54 to the first input terminal of adder 48. With respect to variable x (integer), a clock circuit 56 sends (x+1) synchronized clock pulses CLK.sub.i and x clock pulses CLK.sub.k to registers 36 and 42 of first-stage and second-stage series operators 32 and 38, respectively.
摘要翻译： 具有低成本，小规模电路的第n度函数计算装置，其中不存在乘法器并且允许高速计算操作。 第n度函数计算装置包括串联连接的两个串联运算器32和38，插入在它们之间的加法器44，以及插入在第二级串联运算器38的输出端和装置输出端46之间的加法器48。 常数2a2从恒定发生器50发送到第一级串联运算器32的加法器34的第一输入端。常数（a1-a2）从常数发生器52发送到加法器44的第一输入端。常数a0 从恒定发生器54发送到加法器48的第一输入端。对于可变x（整数），时钟电路56将（x + 1）同步时钟脉冲CLKi和x个时钟脉冲CLKk发送到第一 级和第二级系列操作员32和38。
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公开(公告)号：US5095456A
公开(公告)日：1992-03-10
申请号：US498312
申请日：1990-03-23
申请人： Yiwan Wong , Toshiaki Yoshino , Louis G. Johnson
发明人： Yiwan Wong , Toshiaki Yoshino , Louis G. Johnson
CPC分类号： G06F17/142 , G06F7/4812
摘要： A method for densely packing a complex multiplier for multiplying two complex numbers in the form of (A+jB) and (X+jY) is provided. The complex multiplier consist of two multipliers which perform (A*X), (A*Y), (B*X) and (B*Y) multiplications, and each multiplier has a plurality of partial product generating stages and a partial product summing stage. The method comprises interleaving the plurality of partial product generating stages of the (A*Y) multiplier between the plurality of partial product generating stages of the (A*X) multiplier, forming the partial product summing stage adjacent the interleaved partial product generating stages of the (A*X) and (A*Y) multipliers. Further interleave the plurality of partial product generating stages of the (B*Y) multiplier between the plurality of partial product generating stages of the (B*X) multiplier, and form the partial product summing stage adjacent the interleaved partial product gneerating stages of the (B*X) and (B*Y) multipliers.
摘要翻译： 提供了用于将（A + jB）和（X + jY）形式的两个复数乘以复数乘法器的密集打包的方法。 复数乘法器由执行（A * X），（A * Y），（B * X）和（B * Y）乘法的两个乘法器组成，并且每个乘法器具有多个部分乘积生成阶段和部分乘积求和 阶段。 该方法包括在（A * X）乘法器的多个部分乘积产生级之间交织（A * Y）乘法器的多个部分乘积生成级，形成邻近交错部分乘积生成级的部分乘积求和级 （A * X）和（A * Y）乘数。 进一步交织（B * Y）乘数的多个部分乘积生成阶段在（B * X）乘数的多个部分积生成阶段之间，并且形成邻近于（B * Y）乘法器的交错部分积产阶段的部分乘积求和级 （B * X）和（B * Y）乘数。
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5.发明授权Program conversion program, program conversion apparatus and program conversion method 有权程序转换程序，程序转换装置和程序转换方法公开(公告)号：US08209670B2
公开(公告)日：2012-06-26
申请号：US11336917
申请日：2006-01-23
IPC分类号： G06F9/44
CPC分类号： G06F8/74
摘要： A program conversion program, a program conversion apparatus and a program conversion method that conversions a program having different process according to the content of an argument into a program which facilitate the analysis are provided. The program conversion apparatus includes a dedicated call destination program generating unit that detects the call destination program, an argument for differentiating the processes of the call destination program and the content of the argument from the program group and generates a program for executing only a process according to the content of the argument of the processes of the call destination program as the dedicated call destination program for each argument and each content of the argument, and a call source program rewriting unit that detects the call position for calling the call destination program from the program group and rewrites the call position to call the dedicated call destination program generated by the dedicated call destination program generating unit.
摘要翻译： 提供了一种程序转换程序，程序转换装置和程序转换方法，其将具有根据参数内容的不同进程的程序转换成便于分析的程序。 程序转换装置包括一个专用呼叫目的地程序生成单元，用于检测呼叫目的地程序，用于区分呼叫目的地程序的处理和参数内容与该程序组相关联的参数，并且生成仅执行程序 将呼叫目的地程序的处理的参数的内容作为每个参数的专用呼叫目的地程序和参数的每个内容，以及呼叫源程序重写单元，其从所述呼叫目的地程序中调用呼叫目的地程序 程序组并重写呼叫位置，以呼叫由专用呼叫目的地节目产生单元生成的专用呼叫目的地节目。
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6.发明申请Program conversion program, program conversion apparatus and program conversion method 有权程序转换程序，程序转换装置和程序转换方法公开(公告)号：US20070089099A1
公开(公告)日：2007-04-19
申请号：US11336917
申请日：2006-01-23
IPC分类号： G06F9/45
CPC分类号： G06F8/74
摘要： A program conversion program, a program conversion apparatus and a program conversion method that conversions a program having different process according to the content of an argument into a program which facilitate the analysis are provided. The program conversion apparatus includes a dedicated call destination program generating unit that detects the call destination program, an argument for differentiating the processes of the call destination program and the content of the argument from the program group and generates a program for executing only a process according to the content of the argument of the processes of the call destination program as the dedicated call destination program for each argument and each content of the argument, and a call source program rewriting unit that detects the call position for calling the call destination program from the program group and rewrites the call position to call the dedicated call destination program generated by the dedicated call destination program generating unit.
摘要翻译： 提供了一种程序转换程序，程序转换装置和程序转换方法，其将具有根据参数内容的不同进程的程序转换成便于分析的程序。 程序转换装置包括一个专用呼叫目的地程序生成单元，用于检测呼叫目的地程序，用于区分呼叫目的地程序的处理和参数内容与该程序组相关联的参数，并且生成仅执行程序 将呼叫目的地程序的处理的参数的内容作为每个参数的专用呼叫目的地程序和参数的每个内容，以及呼叫源程序重写单元，其从所述呼叫目的地程序中调用呼叫目的地程序 程序组并重写呼叫位置，以呼叫由专用呼叫目的地节目产生单元生成的专用呼叫目的地节目。
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公开(公告)号：US06459738B1
公开(公告)日：2002-10-01
申请号：US09494105
申请日：2000-01-28
申请人： Qiong Wu , Kwok K. Chau , Toshiaki Yoshino
发明人： Qiong Wu , Kwok K. Chau , Toshiaki Yoshino
IPC分类号： H04N712
CPC分类号： H04N19/423 , H04N19/61
摘要： A decoder for decoding a compressed incoming interruptible bitstream is disclosed. The decoder includes an input register that is capable of receiving a latch command, and that is further capable of latching stored data in a particular state upon receiving the latch command. The decoder also includes decoding logic, such as variable length decoding logic, or run-length decoding logic, in communication with the input register. Further included in the decoder is an output register in communication with decoding logic, that is also capable of receiving the latch command, and that is further capable of latching stored data in a particular state upon receiving the latch command. Finally, the decoder includes a register controller in communication with both the input register and the output register. The register controller is capable of receiving a halt command from the system and, upon receiving the halt command, the register controller sends the latch command to both the input register and the output register.
摘要翻译： 公开了一种用于解码压缩输入可中断比特流的解码器。 解码器包括能够接收锁存命令的输入寄存器，并且还能够在接收到锁存命令时在特定状态下锁存存储的数据。 解码器还包括与输入寄存器通信的诸如可变长度解码逻辑或游程长度解码逻辑的解码逻辑。 进一步包括在解码器中的是与解码逻辑通信的输出寄存器，其也能够接收锁存命令，并且还能够在接收到锁存命令时在特定状态下锁存存储的数据。 最后，解码器包括与输入寄存器和输出寄存器通信的寄存器控制器。 寄存器控制器能够从系统接收到停止命令，并且在接收到停止命令时，寄存器控制器将锁存命令发送到输入寄存器和输出寄存器。
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公开(公告)号：US07839311B2
公开(公告)日：2010-11-23
申请号：US12197133
申请日：2008-08-22
申请人： Yiliang Bao , Toshiaki Yoshino , Kai Wang
发明人： Yiliang Bao , Toshiaki Yoshino , Kai Wang
IPC分类号： H03M7/00
摘要： Techniques for optimizing the Context-based Adaptive Binary Arithmetic Coding (CABAC) bitstream decoding are disclosed. In one configuration, a device has a first processing circuit operative to decode a Context-based Adaptive Binary Arithmetic Coding (CABAC) bitstream into an intermediate signal having a CABAC decoded standard format and a decoded order. A second processing circuit decodes the intermediate signal using a non-CABAC decoding standard. A buffer is provided between the first and second processing circuits to improve processing speeds.
摘要翻译： 公开了用于优化基于上下文的自适应二进制算术编码（CABAC）比特流解码的技术。 在一种配置中，设备具有第一处理电路，其操作以将基于上下文的自适应二进制算术编码（CABAC）比特流解码为具有CABAC解码标准格式和解码顺序的中间信号。 第二处理电路使用非CABAC解码标准解码中间信号。 在第一和第二处理电路之间提供缓冲器以提高处理速度。
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9.发明授权
公开(公告)号：US5742827A
公开(公告)日：1998-04-21
申请号：US556122
申请日：1995-11-09
申请人： Takao Ohkubo , Toshiaki Yoshino , Shigeki Suguta , Masaaki Noro
发明人： Takao Ohkubo , Toshiaki Yoshino , Shigeki Suguta , Masaaki Noro
摘要： The syntax of an input program is analyzed, variables substituted for the substitution sentences from an interim expression thereof are classified into categories by utilizing rules of naming variables or the data structure, and a set of substitution sentences having variables of the same kind substituted for the destinations is picked up and is converted into a table. The syntax is analyzed to obtain a syntax structure and data attribute, and the data flow is analyzed to obtain data flow information. By using such information, the use of the temporary variables in the program is judged and the temporary variables that can be erased are erased. The table conversion and the interim expression from which the temporary variables are erased are replaced by the description of a natural language to form specifications.
摘要翻译： 分析输入程序的语法，通过利用命名变量或数据结构的规则将代替来自其临时表达式的替换句子的变量分类为类别，并且将具有相同种类的变量的替换句替换为 目的地被拾起并被转换成一张桌子。 分析语法以获得语法结构和数据属性，并分析数据流以获取数据流信息。 通过使用这样的信息，可以判断程序中临时变量的使用情况，可擦除的临时变量被删除。 临时变量被删除的表转换和临时表达式被自然语言的描述所取代，以形成规范。
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10.发明授权
公开(公告)号：US5696836A
公开(公告)日：1997-12-09
申请号：US406017
申请日：1995-03-17
申请人： Toshiaki Yoshino , King Pang
发明人： Toshiaki Yoshino , King Pang
摘要： A circuit for calculating a sum of absolute errors for use in full block search matching in a motion estimation processor is disclosed herein, the circuit being easily implemented and capable of running at 54 Mhz. The circuit accesses search window and reference data from memory and loads the data into rows of laterally interacting processing elements having an architecture capable of fast data processing. A sum of absolute errors between all elements of each row of search data and all elements of each row of reference data is calculated, and the absolute error for all rows of processing elements is totalled. From this total sum of absolute error, the motion vector may be predicted for the next frame.
摘要翻译： 这里公开了一种用于计算运动估计处理器中的全块搜索匹配中使用的绝对误差之和的电路，该电路容易实现并且能够以54Mhz运行。 电路从存储器访问搜索窗口和参考数据，并将数据加载到具有能够进行快速数据处理的架构的横向相互作用的处理元件的行中。 计算每行搜索数据的所有元素和每行参考数据的所有元素之间的绝对误差之和，并且总计处理元素的所有行的绝对误差。 根据该绝对误差的总和，可以为下一帧预测运动矢量。
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