公开(公告)号：US07629223B2

公开(公告)日：2009-12-08

申请号：US12292511

申请日：2008-11-20

申请人： Tadashi Narita ,  Katsuo Oshima

发明人： Tadashi Narita ,  Katsuo Oshima

IPC分类号： H01L21/76

CPC分类号： H01L21/76224 ,  H01L21/823481 ,  Y10S438/975

摘要： A method for manufacturing a semiconductor device includes forming a plurality of trenches for element isolation and a plurality of trenches for alignment mark on a substrate. The substrate has an active region. The method also includes laminating an oxide film on the substrate and over both of the trenches. The method also includes etching the oxide film using a resist mask that masks the element isolation trenches, so that the oxide film laminated in the active region and the oxide film laminated in the alignment mark trenches are removed. The method also includes polishing a surface of the substrate to planarize or smooth the surface of the substrate. Accordingly, those portions of the oxide film which project from the substrate surface are eliminated and the oxide film remains only inside the element isolation trenches. This divides the active region into a plurality of individual active regions for the respective semiconductor elements. The method also includes positioning the resist mask using the alignment mark trenches. The resist mask is used to fabricate the semiconductor elements in the active regions of the substrate.

摘要翻译： 一种制造半导体器件的方法包括：在衬底上形成用于元件隔离的多个沟槽和用于对准标记的多个沟槽。 衬底具有活性区域。 该方法还包括在衬底上和两个沟槽上层叠氧化膜。 该方法还包括使用掩模元件隔离沟槽的抗蚀剂掩模来蚀刻氧化膜，从而去除叠层在有源区中的氧化膜和层叠在对准标记沟槽中的氧化膜。 该方法还包括抛光衬底的表面以平坦化或平滑衬底的表面。 因此，从衬底表面突出的氧化膜的那些部分被去除，并且氧化物膜仅保留在元件隔离沟槽内部。 这将有源区域划分成用于各个半导体元件的多个单独的有源区域。 该方法还包括使用对准标记沟槽定位抗蚀剂掩模。 抗蚀剂掩模用于在衬底的有源区域中制造半导体元件。

公开(公告)号：US20090137092A1

公开(公告)日：2009-05-28

申请号：US12292511

申请日：2008-11-20

申请人： Tadashi Narita ,  Katsuo Oshima

发明人： Tadashi Narita ,  Katsuo Oshima

IPC分类号： H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/823481 ,  Y10S438/975

摘要： A method for manufacturing a semiconductor device includes forming a plurality of trenches for element isolation and a plurality of trenches for alignment mark on a substrate. The substrate has an active region. The method also includes laminating an oxide film on the substrate and over both of the trenches. The method also includes etching the oxide film using a resist mask that masks the element isolation trenches, so that the oxide film laminated in the active region and the oxide film laminated in the alignment mark trenches are removed. The method also includes polishing a surface of the substrate to planarize or smooth the surface of the substrate. Accordingly, those portions of the oxide film which project from the substrate surface are eliminated and the oxide film remains only inside the element isolation trenches. This divides the active region into a plurality of individual active regions for the respective semiconductor elements. The method also includes positioning the resist mask using the alignment mark trenches. The resist mask is used to fabricate the semiconductor elements in the active regions of the substrate.

公开(公告)号：US06838643B2

公开(公告)日：2005-01-04

申请号：US10197598

申请日：2002-07-18

申请人： Shouzou Kobayashi ,  Takamitsu Furukawa ,  Keisuke Tanaka ,  Kouhei Shimoyama ,  Akira Watanabe ,  Tadashi Nishimuro ,  Koki Muto ,  Azusa Yanagisawa ,  Katsuo Oshima

发明人： Shouzou Kobayashi ,  Takamitsu Furukawa ,  Keisuke Tanaka ,  Kouhei Shimoyama ,  Akira Watanabe ,  Tadashi Nishimuro ,  Koki Muto ,  Azusa Yanagisawa ,  Katsuo Oshima

IPC分类号： G03F7/30 ,  H01L21/00 ,  H01L21/027 ,  H05B3/00 ,  F27B5/14

CPC分类号： H01L21/67248 ,  H01L21/67109

摘要： An apparatus for baking a semiconductor wafer having a resist pattern thereon includes a baking oven in which the semiconductor wafer is placed and heated, and a first hot plate which is provided in the baking oven to heat an entire bottom surface of the semiconductor wafer. The apparatus also includes a gas supply unit having a gas introducing path, through which the purge gas is introduced into the baking oven, and a gas exhaust path, through which the purge gas is exhausted out of the baking oven. A gas temperature controller controls a temperature of the purge gas in order that the purge gas flowing around a peripheral edge or outer portion of the wafer has a higher temperature than that around the center or inner portion of the wafer.

公开(公告)号：US06455438B1

公开(公告)日：2002-09-24

申请号：US09662855

申请日：2000-09-15

申请人： Azusa Yanagisawa ,  Koki Muto ,  Tadashi Nishimuro ,  Katsuo Oshima ,  Akira Watanabe ,  Akihiko Nara ,  Kouhei Shimoyama ,  Keisuke Tanaka ,  Takamitsu Furukawa ,  Shouzou Kobayashi

发明人： Azusa Yanagisawa ,  Koki Muto ,  Tadashi Nishimuro ,  Katsuo Oshima ,  Akira Watanabe ,  Akihiko Nara ,  Kouhei Shimoyama ,  Keisuke Tanaka ,  Takamitsu Furukawa ,  Shouzou Kobayashi

IPC分类号： H01L2100

CPC分类号： H01L21/0273 ,  G03F7/40 ,  H01L21/31144

摘要： According to the present invention, a semiconductor device is fabricated by the following processes. First, a film to be etched is formed on a semiconductor substrate. On the film to be etched is formed a resist film. Then, a first pattern group including first patterns having a first size and a second pattern group including second patterns arranged outside of the first pattern group are formed by exposure. The resist film is then developed to form openings in the resist film so that the resultant openings correspond to the first and second patterns, respectively. The openings are then made smaller by annealing the resist film. The aforementioned processes enables openings having substantially the same shape to be formed in the film to be etched.

摘要翻译： 根据本发明，通过以下方法制造半导体器件。 首先，在半导体基板上形成被蚀刻的膜。 在被蚀刻的膜上形成抗蚀剂膜。 然后，通过曝光形成包括具有第一尺寸的第一图案和包括布置在第一图案组外部的第二图案的第二图案组的第一图案组。 然后将抗蚀剂膜显影以在抗蚀剂膜中形成开口，使得所得到的开口分别对应于第一和第二图案。 然后通过退火抗蚀剂膜使开口变小。 上述处理使得能够在待蚀刻的膜中形成具有基本相同形状的开口。

公开(公告)号：US06869738B2

公开(公告)日：2005-03-22

申请号：US10305098

申请日：2002-11-27

申请人： Katsuo Oshima ,  Koki Muto

发明人： Katsuo Oshima ,  Koki Muto

IPC分类号： G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G03F7/20 ,  H01L21/027 ,  G03F9/00

CPC分类号： G03F1/36

摘要： The main mask pattern of a photomask is corrected by adding serifs of one type (inner or outer) to a pair of mutually adjacent corners in the pattern, and adding a serif of the opposite type (outer or inner) to the edge between the corners. When the photomask is used to create a resist pattern by photolithography in the fabrication of a semiconductor device, the serifs combine to produce an optical proximity correction that reduces corner rounding and increases edge straightness in the resist pattern.

摘要翻译： 通过将一种类型（内部或外部）的衬线添加到图案中的一对相互相邻的角部来校正光掩模的主掩模图案，并且将相反类型（外部或内部）的衬线添加到角部之间的边缘 。 当光掩模用于在半导体器件的制造中通过光刻产生抗蚀剂图案时，衬线组合以产生光学邻近校正，其减少拐角圆角并增加抗蚀剂图案中的边缘直线度。