公开(公告)号：US20110037103A1

公开(公告)日：2011-02-17

申请号：US12852259

申请日：2010-08-06

申请人： Tadashi YAMAGUCHI ,  Keiichiro KASHIHARA ,  Toshiaki TSUTSUMI ,  Tomonori OKUDAIRA ,  Kotaro KIHARA

发明人： Tadashi YAMAGUCHI ,  Keiichiro KASHIHARA ,  Toshiaki TSUTSUMI ,  Tomonori OKUDAIRA ,  Kotaro KIHARA

IPC分类号： H01L27/105 ,  H01L21/8239 ,  H01L29/04

CPC分类号： H01L27/105 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1116 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

摘要： To improve performance of a semiconductor device. Over a semiconductor substrate, a plurality of p-channel type MISFETs for logic, a plurality of n-channel type MISFETs for logic, a plurality of p-channel type MISFETs for memory, and a plurality of n-channel type MISFETs for memory are mixedly mounted. At least a part of the p-channel type MISFETs for logic have each a source/drain region constituted by silicon-germanium, and all the n-channel type MISFETs for logic have each a source/drain region constituted by silicon. All the p-channel type MISFETs for memory have each a source/drain region constituted by silicon, and all the n-channel type MISFETs for memory have each a source/drain region constituted by silicon.

摘要翻译： 提高半导体器件的性能。 在半导体衬底上，用于逻辑的多个p沟道型MISFET，用于逻辑的多个n沟道型MISFET，用于存储器的多个p沟道型MISFET和用于存储器的多个n沟道型MISFET， 混合安装。 用于逻辑的p沟道型MISFET的至少一部分具有由硅 - 锗构成的源极/漏极区域，并且用于逻辑的所有n沟道型MISFET具有由硅构成的源极/漏极区域。 用于存储器的所有p沟道型MISFET具有由硅构成的源极/漏极区域，并且用于存储器的所有n沟道型MISFET具有由硅构成的源极/漏极区域。

公开(公告)号：US20090291537A1

公开(公告)日：2009-11-26

申请号：US12510026

申请日：2009-07-27

申请人： Tadashi YAMAGUCHI ,  Keiichiro KASHIHARA ,  Tomonori OKUDAIRA ,  Toshiaki TSUTSUMI

发明人： Tadashi YAMAGUCHI ,  Keiichiro KASHIHARA ,  Tomonori OKUDAIRA ,  Toshiaki TSUTSUMI

IPC分类号： H01L21/336

CPC分类号： H01L29/045 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7848

摘要： A method of manufacturing a semiconductor device, including the steps of preparing a silicon substrate which has a main surface whose plane direction is a surface (100); forming an n channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) which has a gate electrode, a source region, a drain region and a channel whose channel length direction is parallel to a crystal orientation of the silicon substrate; and forming NiSi over the gate electrode and NiSi2 over the source region and the drain region at the same steps.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：制备具有平面方向为表面（100）的主表面的硅衬底; 形成具有栅电极，源极区，漏极区和沟道长度方向平行于硅衬底的晶体取向<100°的沟道的n沟道MISFET（金属绝缘体半导体场效应晶体管）; 并且在相同的步骤上在源极区域和漏极区域上在栅电极和NiSi 2上形成NiSi。

公开(公告)号：US20070284671A1

公开(公告)日：2007-12-13

申请号：US11759564

申请日：2007-06-07

申请人： Toshiaki TSUTSUMI ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

发明人： Toshiaki TSUTSUMI ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

IPC分类号： H01L29/94 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/28097 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/66545

摘要： Gate electrodes made of polysilicon film are isolated and face each other by way of a side wall spacer portion that fills a gap formed above an isolation insulating film at the boundary of NMIS region and PMIS region. A first metal film is formed on one of the gate electrodes, and an inhomogeneous second metal film is formed on the other of the gate electrodes. The both gate electrodes become inhomogeneous metal silicide gates through the promotion of silicide reaction by heat treatment. The mutual diffusion of metal atoms from the metal film to the gate electrode is suppressed by the interposition of the side wall spacer portion being an insulating film.

摘要翻译： 由多晶硅膜制成的栅电极被隔离并且通过填充在NMIS区域和PMIS区域的边界处的隔离绝缘膜上形成的间隙的侧壁间隔部分相互面对。 在一个栅电极上形成第一金属膜，另一个栅电极上形成非均匀的第二金属膜。 通过热处理促进硅化物反应，两个栅电极成为不均匀的金属硅化物栅极。 通过插入作为绝缘膜的侧壁间隔物部分来抑制金属膜从金属膜到栅电极的相互扩散。

公开(公告)号：US20090283909A1

公开(公告)日：2009-11-19

申请号：US12413980

申请日：2009-03-30

申请人： Toshiaki TSUTSUMI ,  Tomonori OKUDAIRA ,  Keiichiro KASHIHARA ,  Tadashi TAMAGUCHI

发明人： Toshiaki TSUTSUMI ,  Tomonori OKUDAIRA ,  Keiichiro KASHIHARA ,  Tadashi TAMAGUCHI

IPC分类号： H01L23/52 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L23/485 ,  H01L21/28518 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.

摘要翻译： 提供了具有金属硅化物层的半导体器件，其可以抑制器件的故障和功率消耗的增加。 半导体器件具有包含硅并具有主表面的半导体衬底，形成在半导体衬底的主表面中的第一和第二杂质扩散层，形成在第二杂质扩散层上的金属硅化物，以及氮化硅膜和第一 层间绝缘膜依次层叠在金属硅化物上。 在半导体器件中，形成穿过氮化硅膜和第一层间绝缘膜并到达金属硅化物表面的接触孔。 位于接触孔正下方的金属硅化物的一部分的厚度小于位于接触孔周围的金属硅化物的一部分的厚度。