公开(公告)号：US20110207317A1

公开(公告)日：2011-08-25

申请号：US13053733

申请日：2011-03-22

申请人： Toshiaki Tsutsumi ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

发明人： Toshiaki Tsutsumi ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

IPC分类号： H01L21/768

CPC分类号： H01L23/485 ,  H01L21/28518 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.

摘要翻译： 提供了具有金属硅化物层的半导体器件，其可以抑制器件的故障和功率消耗的增加。 半导体器件具有包含硅并具有主表面的半导体衬底，形成在半导体衬底的主表面中的第一和第二杂质扩散层，形成在第二杂质扩散层上的金属硅化物，以及氮化硅膜和第一 层间绝缘膜依次层叠在金属硅化物上。 在半导体器件中，形成穿过氮化硅膜和第一层间绝缘膜并到达金属硅化物表面的接触孔。 位于接触孔正下方的金属硅化物的一部分的厚度小于位于接触孔周围的金属硅化物的一部分的厚度。

公开(公告)号：US20110037103A1

公开(公告)日：2011-02-17

申请号：US12852259

申请日：2010-08-06

申请人： Tadashi YAMAGUCHI ,  Keiichiro KASHIHARA ,  Toshiaki TSUTSUMI ,  Tomonori OKUDAIRA ,  Kotaro KIHARA

发明人： Tadashi YAMAGUCHI ,  Keiichiro KASHIHARA ,  Toshiaki TSUTSUMI ,  Tomonori OKUDAIRA ,  Kotaro KIHARA

IPC分类号： H01L27/105 ,  H01L21/8239 ,  H01L29/04

CPC分类号： H01L27/105 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1116 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

摘要： To improve performance of a semiconductor device. Over a semiconductor substrate, a plurality of p-channel type MISFETs for logic, a plurality of n-channel type MISFETs for logic, a plurality of p-channel type MISFETs for memory, and a plurality of n-channel type MISFETs for memory are mixedly mounted. At least a part of the p-channel type MISFETs for logic have each a source/drain region constituted by silicon-germanium, and all the n-channel type MISFETs for logic have each a source/drain region constituted by silicon. All the p-channel type MISFETs for memory have each a source/drain region constituted by silicon, and all the n-channel type MISFETs for memory have each a source/drain region constituted by silicon.

摘要翻译： 提高半导体器件的性能。 在半导体衬底上，用于逻辑的多个p沟道型MISFET，用于逻辑的多个n沟道型MISFET，用于存储器的多个p沟道型MISFET和用于存储器的多个n沟道型MISFET， 混合安装。 用于逻辑的p沟道型MISFET的至少一部分具有由硅 - 锗构成的源极/漏极区域，并且用于逻辑的所有n沟道型MISFET具有由硅构成的源极/漏极区域。 用于存储器的所有p沟道型MISFET具有由硅构成的源极/漏极区域，并且用于存储器的所有n沟道型MISFET具有由硅构成的源极/漏极区域。

公开(公告)号：US07872314B2

公开(公告)日：2011-01-18

申请号：US12727334

申请日：2010-03-19

申请人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

发明人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

IPC分类号： H01L23/62

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.

摘要翻译： 离子（含有F，Si，C，Ge，Ne，Ar和Kr中的至少一个）注入N沟道型MISFET的N型源极区域和N型漏极区域，P沟道型MISFET为 被掩模层覆盖。 然后，对N沟道型MISFET和P沟道型MISFET的各栅电极，源极区和漏极区进行硅化（含有Ni，Ti，Co，Pd，Pt和Er中的至少一种）。 这可以抑制N沟道型MISFET中的漏 - 漏泄漏电流（衬底泄漏电流），而不会降低P沟道型MISFET中的漏 - 漏泄漏电流。

公开(公告)号：US07696050B2

公开(公告)日：2010-04-13

申请号：US11537208

申请日：2006-09-29

申请人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

发明人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

IPC分类号： H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.

摘要翻译： 离子（含有F，Si，C，Ge，Ne，Ar和Kr中的至少一个）注入N沟道型MISFET的N型源极区域和N型漏极区域，P沟道型MISFET为 被掩模层覆盖。 然后，对N沟道型MISFET和P沟道型MISFET的各栅电极，源极区和漏极区进行硅化（含有Ni，Ti，Co，Pd，Pt和Er中的至少一种）。 这可以抑制N沟道型MISFET中的漏 - 漏泄漏电流（衬底泄漏电流），而不会降低P沟道型MISFET中的漏 - 漏泄漏电流。

公开(公告)号：US06535781B1

公开(公告)日：2003-03-18

申请号：US09520710

申请日：2000-03-08

申请人： Toshiaki Tsutsumi

发明人： Toshiaki Tsutsumi

IPC分类号： G06F1900

CPC分类号： H01J37/28 ,  G01N21/9501 ,  G01N2021/8864 ,  G05B2219/33263 ,  G05B2219/45031 ,  H01J2237/15 ,  H01J2237/2817

摘要： In an apparatus for inspecting and analyzing a particle on a wafer, which causes defect of an integrated circuit, the invention aims to improve the precision of the coordinate of the particle to facilitate the analysis of the particle. As a result, the generation of the particle can be reduced and the yield of the integrated circuit can be increased. A coordinate modifying apparatus of the invention includes a parameter calculating unit 40 for calculating a coordinate modification parameter, a parameter memory 60 for storing the coordinate modification parameter, and a coordinate modifying unit 70 for correcting the coordinate using the coordinate modification parameter.

摘要翻译： 在用于检查和分析晶片上的颗粒的装置中，导致集成电路的缺陷，本发明旨在提高颗粒坐标的精度以便于分析颗粒。 结果，可以减少颗粒的产生，并且可以提高集成电路的产量。本发明的坐标修改装置包括：用于计算坐标修改参数的参数计算单元40，用于存储坐标修改参数的参数存储器60 坐标修正参数，以及坐标修改单元70，用于使用坐标修改参数校正坐标。

公开(公告)号：US6087727A

公开(公告)日：2000-07-11

申请号：US683537

申请日：1996-07-15

申请人： Toshiaki Tsutsumi

发明人： Toshiaki Tsutsumi

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/8232 ,  H01L21/8242 ,  H01L23/485 ,  H01L27/108 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L27/10873 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/8232 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S257/903 ,  Y10S257/906 ,  Y10S257/907 ,  Y10S257/908

摘要： An object is to provide a structure of a semiconductor device which allows higher degree of integration both in vertical and horizontal directions, and to provide manufacturing method therefor. The semiconductor device includes source.drain electrodes connected to n.sup.- and n.sup.+ source.drain regions of an MISFET and has a function as a part of a bit line, and a gate electrode connected to a first interconnection as a word line. Electrodes are insulated from each other by a sidewall insulating film, silicon oxide film or a silicon nitride film provided inbetween. Since the word line and the bit line do not cross in the same plane, the difference in level in the vertical direction can be reduced.

摘要翻译： 本发明的目的是提供一种半导体器件的结构，其能够在垂直和水平方向上实现更高程度的集成，并提供其制造方法。 半导体器件包括连接到MISFET的n +和n +源极区域的源极电极，并且具有作为位线的一部分的功能，以及连接到作为字线的第一互连的栅电极。 电极通过其间设置的侧壁绝缘膜，氧化硅膜或氮化硅膜彼此绝缘。 由于字线和位线在同一平面上不交叉，所以可以减小垂直方向上的电平差。

公开(公告)号：US09252793B2

公开(公告)日：2016-02-02

申请号：US13990030

申请日：2010-11-29

申请人： Toshiaki Tsutsumi ,  Yoshihiro Funato ,  Tomonori Okudaira ,  Tadato Yamagata ,  Akihisa Uchida ,  Takeshi Terasaki ,  Tomohisa Suzuki ,  Yoshiharu Kanegae

发明人： Toshiaki Tsutsumi ,  Yoshihiro Funato ,  Tomonori Okudaira ,  Tadato Yamagata ,  Akihisa Uchida ,  Takeshi Terasaki ,  Tomohisa Suzuki ,  Yoshiharu Kanegae

IPC分类号： H03L7/24 ,  H01L23/522 ,  H01L27/06 ,  H01L23/31 ,  H01L23/00

CPC分类号： H03B5/24 ,  H01L23/3107 ,  H01L23/5228 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/24 ,  H01L2224/05554 ,  H01L2224/06179 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/01015 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H03L7/24 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage. The reference resistor is formed of a plurality of resistors, which extend in a first (Y) direction orthogonal to a first side, inside a first region (RG1, RG2, RG3, and RG4) surrounded by the first side (S1, S2, S3, and S4) of a main surface of the semiconductor chip (CP1), a first line (42, 43, 44, and 45) connecting between one end of the first side and the center (CT1) of the main surface of the semiconductor chip, and a second line (42, 43, 44, and 45) connecting between the other end of the first side and the center of the main surface of the semiconductor chip.

公开(公告)号：US20130314165A1

公开(公告)日：2013-11-28

申请号：US13990030

申请日：2010-11-29

申请人： Toshiaki Tsutsumi ,  Yoshihiro Funato ,  Tomonori Okudaira ,  Tadato Yamagata ,  Akihisa Uchida ,  Takeshi Terasaki ,  Tomohisa Suzuki ,  Yoshiharu Kanegae

发明人： Toshiaki Tsutsumi ,  Yoshihiro Funato ,  Tomonori Okudaira ,  Tadato Yamagata ,  Akihisa Uchida ,  Takeshi Terasaki ,  Tomohisa Suzuki ,  Yoshiharu Kanegae

IPC分类号： H03L7/24

CPC分类号： H03B5/24 ,  H01L23/3107 ,  H01L23/5228 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/24 ,  H01L2224/05554 ,  H01L2224/06179 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/01015 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H03L7/24 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage. The reference resistor is formed of a plurality of resistors, which extend in a first (Y) direction orthogonal to a first side, inside a first region (RG1, RG2, RG3, and RG4) surrounded by the first side (S1, S2, S3, and S4) of a main surface of the semiconductor chip (CP1), a first line (42, 43, 44, and 45) connecting between one end of the first side and the center (CT1) of the main surface of the semiconductor chip, and a second line (42, 43, 44, and 45) connecting between the other end of the first side and the center of the main surface of the semiconductor chip.

摘要翻译： 通过用树脂密封具有利用参考电阻器的振荡电路的半导体芯片（CP1）形成半导体器件。 振荡电路利用参考电阻产生参考电流，根据该参考电流产生电压和振荡单元的振荡频率，并且振荡单元根据所产生的电压以频率振荡。 参考电阻器由多个电阻器构成，该多个电阻器在与第一侧面正交的第一（Y）方向上在由第一侧（S1，S2，RG3，RG3和RG4）包围的第一区域（RG1，RG2， S3和S4），连接在第一侧的一端与第一侧的主表面的中心（CT1）之间的第一线（42,43,44和45） 半导体芯片和连接在第一侧的另一端和半导体芯片的主表面的中心之间的第二线（42,43,44和45）。

公开(公告)号：US20110171897A1

公开(公告)日：2011-07-14

申请号：US13061864

申请日：2009-08-24

申请人： Toshiaki Tsutsumi ,  Takayuki Arai ,  Masayuki Murase ,  Daisuke Araki

发明人： Toshiaki Tsutsumi ,  Takayuki Arai ,  Masayuki Murase ,  Daisuke Araki

IPC分类号： B60H1/26

CPC分类号： B60H1/00849 ,  B60H1/00671 ,  B60H2001/00085 ,  B60H2001/00614 ,  B60H2001/00721

摘要： A vehicle air conditioner provided with an airflow structure for an intake box, wherein, in an HVAC comprising, in an intake box, a control device for controlling the number of rotation, the control device is reliably cooled by airflow regardless of the ratio of mixing between internal air and external air. A vehicle air conditioner of center-concentrated type, wherein a control device (6) for controlling the number of rotation is mounted to a vehicle interior-side wall surface inside an intake box (2) and wherein an air delivery guide (22) is provided in the intake box (2), the air delivery guide (22) delivering to the control device (6) a part of air introduced from a direction crossing the direction of opening of a suction opening (7) of a blower (8).

摘要翻译： 一种车辆空调装置，其具有用于进气箱的气流结构，其中，在HVAC中，在进气箱中包括用于控制旋转次数的控制装置，所述控制装置通过气流可靠地冷却，而与混合比无关 内部空气和外部空气之间。 一种中心集中式的车辆用空调装置，其特征在于，在进气箱（2）的内部的车辆内侧壁面上安装有用于控制旋转数的控制装置（6），其中，空气排出导向件（22）为 设置在所述进气箱（2）中的所述空气输送引导件（22）将从与鼓风机（8）的吸入口（7）的打开方向相交叉的方向引入的空气的一部分输送到所述控制装置（6） 。

公开(公告)号：US20070114666A1

公开(公告)日：2007-05-24

申请号：US11650978

申请日：2007-01-09

申请人： Takeshi Kamino ,  Toshiaki Tsutsumi ,  Shuji Kodama ,  Takio Ohno

发明人： Takeshi Kamino ,  Toshiaki Tsutsumi ,  Shuji Kodama ,  Takio Ohno

IPC分类号： H01L23/48

CPC分类号： H01L28/24 ,  H01L23/26 ,  H01L27/0802 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a semiconductor device with a configuration in which a dummy silicide area 11 is provided in the vicinity of a non-silicide area 2 to easily capture residual refractory metals, resulting in an improved yield by preventing the trapping of residual refractory metals into a non-silicide area and thereby reducing a junction leakage within the non-silicide area.