公开(公告)号：US08343827B2

公开(公告)日：2013-01-01

申请号：US13182750

申请日：2011-07-14

申请人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Yoji Kawasaki

发明人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Yoji Kawasaki

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

摘要： In a CMIS device, to improve the operating characteristics of an n-channel electric field transistor that is formed by using a strained silicon technique, without degrading the operating characteristics of a p-channel field effect transistor. After forming a source/drain (an n-type extension region and an n-type diffusion region) of an nMIS and a source/drain (a p-type extension region and a p-type diffusion region) of a pMIS, the each source/drain having a desired concentration profile and resistance, a Si:C layer having a desired amount of strain is formed in the n-type diffusion region, and thus the optimum parasitic resistance and the optimum amount of strain in the Si:C layer are obtained in the source/drain of the nMIS. Moreover, by performing a heat treatment in forming the Si:C layer in a short time equal to or shorter than 1 millisecond, a change in the concentration profile of the respective p-type impurities of the already-formed p-type extension region and p-type diffusion region is suppressed.

摘要翻译： 在CMIS器件中，为了改善通过使用应变硅技术形成的n沟道电场晶体管的工作特性，而不降低p沟道场效应晶体管的工作特性。 在形成pISIS的nMIS和源极/漏极（p型延伸区域和p型扩散区域）的源极/漏极（n型延伸区域和n型扩散区域）之后， 源极/漏极具有所需的浓度分布和电阻，在n型扩散区域中形成具有所需量的应变的Si：C层，因此Si：C层中的最佳寄生电阻和最佳应变量 在nMIS的源/漏中获得。 此外，通过在等于或短于1毫秒的短时间内形成Si：C层进行热处理，已经形成的p型延伸区域的各个p型杂质的浓度分布的变化和 p型扩散区被抑制。

公开(公告)号：US20100171183A1

公开(公告)日：2010-07-08

申请号：US12727334

申请日：2010-03-19

申请人： Tadashi YAMAGUCHI ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

发明人： Tadashi YAMAGUCHI ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

IPC分类号： H01L27/092

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.

摘要翻译： 离子（含有F，Si，C，Ge，Ne，Ar和Kr中的至少一个）注入N沟道型MISFET的N型源极区域和N型漏极区域，P沟道型MISFET为 被掩模层覆盖。 然后，对N沟道型MISFET和P沟道型MISFET的各栅电极，源极区和漏极区进行硅化（含有Ni，Ti，Co，Pd，Pt和Er中的至少一种）。 这可以抑制N沟道型MISFET中的漏 - 漏泄漏电流（衬底泄漏电流），而不会降低P沟道型MISFET中的漏 - 漏泄漏电流。

公开(公告)号：US20090291537A1

公开(公告)日：2009-11-26

申请号：US12510026

申请日：2009-07-27

申请人： Tadashi YAMAGUCHI ,  Keiichiro KASHIHARA ,  Tomonori OKUDAIRA ,  Toshiaki TSUTSUMI

发明人： Tadashi YAMAGUCHI ,  Keiichiro KASHIHARA ,  Tomonori OKUDAIRA ,  Toshiaki TSUTSUMI

IPC分类号： H01L21/336

CPC分类号： H01L29/045 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7848

摘要： A method of manufacturing a semiconductor device, including the steps of preparing a silicon substrate which has a main surface whose plane direction is a surface (100); forming an n channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) which has a gate electrode, a source region, a drain region and a channel whose channel length direction is parallel to a crystal orientation of the silicon substrate; and forming NiSi over the gate electrode and NiSi2 over the source region and the drain region at the same steps.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：制备具有平面方向为表面（100）的主表面的硅衬底; 形成具有栅电极，源极区，漏极区和沟道长度方向平行于硅衬底的晶体取向<100°的沟道的n沟道MISFET（金属绝缘体半导体场效应晶体管）; 并且在相同的步骤上在源极区域和漏极区域上在栅电极和NiSi 2上形成NiSi。

公开(公告)号：US20090283909A1

公开(公告)日：2009-11-19

申请号：US12413980

申请日：2009-03-30

申请人： Toshiaki TSUTSUMI ,  Tomonori OKUDAIRA ,  Keiichiro KASHIHARA ,  Tadashi TAMAGUCHI

发明人： Toshiaki TSUTSUMI ,  Tomonori OKUDAIRA ,  Keiichiro KASHIHARA ,  Tadashi TAMAGUCHI

IPC分类号： H01L23/52 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L23/485 ,  H01L21/28518 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.

摘要翻译： 提供了具有金属硅化物层的半导体器件，其可以抑制器件的故障和功率消耗的增加。 半导体器件具有包含硅并具有主表面的半导体衬底，形成在半导体衬底的主表面中的第一和第二杂质扩散层，形成在第二杂质扩散层上的金属硅化物，以及氮化硅膜和第一 层间绝缘膜依次层叠在金属硅化物上。 在半导体器件中，形成穿过氮化硅膜和第一层间绝缘膜并到达金属硅化物表面的接触孔。 位于接触孔正下方的金属硅化物的一部分的厚度小于位于接触孔周围的金属硅化物的一部分的厚度。

公开(公告)号：US20080121950A1

公开(公告)日：2008-05-29

申请号：US11771340

申请日：2007-06-29

申请人： Tadashi YAMAGUCHI ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

发明人： Tadashi YAMAGUCHI ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

IPC分类号： H01L29/04

CPC分类号： H01L29/045 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7848

摘要： Even if it is a case where the silicide region of nickel or a nickel alloy is formed in the source and drain of n channel MISFET, the semiconductor device in which OFF leakage current does not increase easily is realized.The channel length direction of n channel MISFET where the silicide region of nickel or a nickel alloy was formed on the source and the drain is arranged so that it may become parallel to the crystal orientation of a semiconductor substrate. Since it is hard to extend the silicide region of nickel or a nickel alloy in the direction of crystal orientation , even if it is a case where the silicide region of nickel or a nickel alloy is formed in the source and drain of n channel MISFET, the semiconductor device in which OFF leakage current does not increase easily is obtained.

摘要翻译： 即使是在n沟道MISFET的源极和漏极中形成镍或镍合金的硅化物区域的情况，也可以实现OFF泄漏电流容易增加的半导体器件。 在源极和漏极上形成镍或镍合金的硅化物区域的n沟道MISFET的沟道长度方向被布置成使其可以平行于半导体衬底的晶体取向<100>。 由于难以在晶体取向<100>的方向上延伸镍或镍合金的硅化物区域，所以即使在镍或镍合金的硅化物区域形成在n的源极和漏极中的情况 通道MISFET，可以容易地提高OFF漏电流的半导体装置。

公开(公告)号：US06479856B1

公开(公告)日：2002-11-12

申请号：US09435214

申请日：1999-11-05

申请人： Keiichiro Kashihara

发明人： Keiichiro Kashihara

IPC分类号： H01L27108

CPC分类号： H01L28/55 ,  H01L27/10814 ,  H01L28/75

摘要： A Layered product (70) is formed on a high-dielectric-constant layer (64). The layered product has a layered structure consisting of an upper electrode (71), a barrier layer (72), a stopper layer (73) and an adhesion layer (74) in this order from the near side of the high-dielectric-constant layer (64). For the high-dielectric-constant layer (64), the upper electrode (71), the barrier layer (72), the stopper layer (73) and the adhesion layer (74), BST, Pt or PtOa, TiN or TiSiN, PtSixOyNz (0

摘要翻译： 在高介电常数层（64）上形成层状产物（70）。 层叠体的高介电常数的近侧依次具有上部电极（71），阻挡层（72），阻挡层（73）和粘附层（74）的层叠结构 层（64）。 对于高介电常数层（64），上电极（71），阻挡层（72），阻挡层（73）和粘附层（74），BST，Pt或PtOa，TiN或TiSiN， 分别使用PtSixOyNz（0

公开(公告)号：US5753527A

公开(公告)日：1998-05-19

申请号：US613555

申请日：1996-03-11

申请人： Hiromi Itoh ,  Tomonori Okudaira ,  Keiichiro Kashihara

发明人： Hiromi Itoh ,  Tomonori Okudaira ,  Keiichiro Kashihara

IPC分类号： H01L27/10 ,  H01L27/108 ,  H01L21/70

CPC分类号： H01L27/10808

摘要： A first interlayer insulating film having a second contact hole is formed on a main surface of a semiconductor substrate 1 in a peripheral circuitry. A second plug electrode of the same material as a first plug electrode in a memory cell array is formed in the second contact hole. A pad layer is formed over the second plug electrode and a top surface of the first interlayer insulating film. The pad layer and a capacitor lower electrode are made of the same material. The pad layer is covered with the second interlayer insulating film. A third contact hole is formed at a portion of the second interlayer insulating film located above the pad layer. A first aluminum interconnection layer is formed in the third contact hole. Thereby, a contact can be formed easily between the interconnection layer and the main surface of the semiconductor substrate in the peripheral circuitry of a DRAM, and a manufacturing process can be simplified.

摘要翻译： 具有第二接触孔的第一层间绝缘膜形成在外围电路中的半导体衬底1的主表面上。 在第二接触孔中形成有与存储单元阵列中的第一插头电极相同材料的第二插头电极。 在第二插头电极和第一层间绝缘膜的顶表面上形成衬垫层。 焊盘层和电容器下电极由相同的材料制成。 衬垫层被第二层间绝缘膜覆盖。 在位于焊盘层上方的第二层间绝缘膜的一部分处形成第三接触孔。 在第三接触孔中形成第一铝互连层。 因此，可以在DRAM的外围电路中的互连层和半导体衬底的主表面之间容易地形成接触，并且可以简化制造工艺。

公开(公告)号：US5693553A

公开(公告)日：1997-12-02

申请号：US689761

申请日：1996-08-13

申请人： Keiichiro Kashihara ,  Hiromi Itoh

发明人： Keiichiro Kashihara ,  Hiromi Itoh

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L21/70

CPC分类号： H01L27/10852 ,  H01L27/11502 ,  Y10S257/90

摘要： An object of the invention is to provide a capacitor having good anti-leak characteristics and good breakdown voltage characteristics. A transfer gate transistor having source/drain regions is formed on a surface of a silicon substrate. There is provided a lower electrode layer connected to the source/drain region through a plug layer which fills a contact hole formed at an interlayer insulating film. On the lower electrode layer, there is formed a capacitor insulating layer which includes a ferroelectric layer and exposes at least a sidewall surface of the lower electrode layer. The exposed sidewall surface of the lower electrode layer is covered with a sidewall insulating layer which is formed on a top surface of the interlayer insulating film and has a sidewall spacer configuration. The lower electrode layer is covered with an upper electrode layer with the sidewall insulating layer and capacitor insulating layer therebetween.

摘要翻译： 本发明的目的是提供具有良好的防漏电特性和良好的击穿电压特性的电容器。 具有源极/漏极区域的传输栅极晶体管形成在硅衬底的表面上。 提供了一个下电极层，该下电极层通过填充形成在层间绝缘膜上的接触孔的插塞层连接到源/漏区。 在下电极层上形成电容绝缘层，该电容器绝缘层包括铁电体层，并暴露至少下电极层的侧壁表面。 下电极层的露出的侧壁表面被形成在层间绝缘膜的顶表面上并具有侧壁间隔物构造的侧壁绝缘层覆盖。 下电极层覆盖有上电极层，其间具有侧壁绝缘层和电容器绝缘层。

公开(公告)号：US5572052A

公开(公告)日：1996-11-05

申请号：US374890

申请日：1995-01-19

申请人： Keiichiro Kashihara ,  Tomonori Okudaira ,  Hiromi Itoh

发明人： Keiichiro Kashihara ,  Tomonori Okudaira ,  Hiromi Itoh

IPC分类号： H01L27/115 ,  H01L29/78 ,  H01L29/92 ,  H01L29/94 ,  G11C11/22 ,  H01G4/06 ,  H01G4/20

CPC分类号： H01L27/11502 ,  H01L29/78391 ,  H01L29/92 ,  H01L29/94

摘要： In an electronic device using lead zirconate titanate (PZT) or lanthanum lead zirconate titanate (PLZT) as the main insulating material, a PZT film or a PLZT film is formed on a sub-insulating layer consisting essentially of lead titanate, lanthanum lead titanate, barium titanate, strontium titanate, barium strontium titanate, lead zirconate, or lanthanum lead zirconate. In an MIS structure, a semiconductor, the sub-insulating layer, the PZT film and metal are deposited in order. In a capacitor, the sub-insulating layer and the PZT film are sandwiched between a pair of electrodes. The sub-insulating layer improves crystallinity of PZT or PLZT, and the dielectric constant. An oxide of Pb, La, Zr or Ti can be added as the sub-insulating layer in order to further suppress current leakage.

摘要翻译： 在使用锆钛酸铅（PZT）或锆钛酸镧铅（PLZT）作为主要绝缘材料的电子器件中，在主要由钛酸铅，钛酸镧铅，钛酸铅等构成的基础绝缘层上形成PZT膜或PLZT膜， 钛酸钡，钛酸锶，钛酸锶钡，锆酸铅或锆酸镧铅。 在MIS结构中，依次沉积半导体，次绝缘层，PZT膜和金属。 在电容器中，副绝缘层和PZT膜夹在一对电极之间。 亚绝缘层提高了PZT或PLZT的结晶度和介电常数。 可以添加Pb，La，Zr或Ti的氧化物作为副绝缘层，以进一步抑制电流泄漏。

公开(公告)号：US5442213A

公开(公告)日：1995-08-15

申请号：US255854

申请日：1994-06-07

申请人： Tomonori Okudaira ,  Takeharu Kuroiwa ,  Nobuo Fujiwara ,  Keiichiro Kashihara

发明人： Tomonori Okudaira ,  Takeharu Kuroiwa ,  Nobuo Fujiwara ,  Keiichiro Kashihara

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L23/522 ,  H01L27/04 ,  H01L27/105 ,  G11C11/24

CPC分类号： H01L27/10852 ,  H01L21/3205 ,  H01L28/40 ,  H01L28/55 ,  Y10S257/915 ,  Y10S438/978

摘要： According to a semiconductor device and a method of manufacturing thereof, a sidewall spacer is formed at a sidewall of a contact hole, in a recess portion defined by the sidewall of the contact hole and a buried conductive layer, having a film thickness gradually increasing from a top face corner of an interlayer insulation film to the surface of the buried conductive layer. Therefore, a semiconductor device that can achieve favorable breakdown voltage and anti-leak characteristics between a lower electrode layer and an upper electrode layer forming a capacitor of a DRAM.

摘要翻译： 根据半导体器件及其制造方法，在由接触孔的侧壁限定的凹部和埋入导电层的接触孔的侧壁处形成侧壁间隔物，其中膜厚度从 层间绝缘膜的顶面角到掩埋导电层的表面。 因此，可以在形成DRAM的电容器的下电极层和上电极层之间实现良好的击穿电压和防漏电特性的半导体装置。