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    Cell structure of non-volatile memory device and method for fabricating the same
    1.
    发明申请
    Cell structure of non-volatile memory device and method for fabricating the same 失效
    非易失性存储器件的单元结构及其制造方法

    公开(公告)号：US20060076608A1

    公开(公告)日：2006-04-13

    申请号：US11281471

    申请日：2005-11-18

    申请人： Tae-Jung Lee ,  Byung-Sun Kim ,  Joon-Hyung Lee

    发明人： Tae-Jung Lee ,  Byung-Sun Kim ,  Joon-Hyung Lee

    IPC分类号： H01L29/788

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

    摘要： A cell structure of a non-volatile memory device, which uses a nitride layer as a floating gate spacer, includes a gate stack and a floating gate transistor formed over a semiconductor substrate. The gate stack includes a first portion of a floating gate, a control gate formed over the first portion of the floating gate, and a non-nitride spacer adjacent to sidewalls of the first portion of floating gate. The floating gate transistor includes a second portion of the floating gate, which substantially overlaps a source and/or drain formed in the substrate. The application of ultraviolet rays to the non-nitride spacer of a programmed cell can causes the second portion of the floating gate to discharge, thereby easily erasing the programmed cell.

    摘要翻译： 使用氮化物层作为浮动栅极隔离物的非易失性存储器件的单元结构包括形成在半导体衬底上的栅极堆叠和浮置栅极晶体管。 栅极堆叠包括浮置栅极的第一部分，形成在浮置栅极的第一部分上的控制栅极以及与浮动栅极的第一部分的侧壁相邻的非氮化物间隔物。 浮栅晶体管包括浮置栅极的第二部分，其基本上与衬底中形成的源极和/或漏极重叠。 将紫外线施加到编程单元的非氮化物间隔物可能导致浮栅的第二部分放电，从而容易地擦除编程的单元。

    Dual port semiconductor memory device
    2.
    发明授权
    Dual port semiconductor memory device 有权
    双端口半导体存储器件

    公开(公告)号：US07120080B2

    公开(公告)日：2006-10-10

    申请号：US10751178

    申请日：2004-01-02

    申请人： Tae-Jung Lee ,  Byung-Sun Kim ,  Joon-Hyung Lee

    发明人： Tae-Jung Lee ,  Byung-Sun Kim ,  Joon-Hyung Lee

    IPC分类号： G11C8/00 ,  G11C5/06 ,  G11C11/00 ,  G06F12/00 ,  G06F13/28

    CPC分类号： H01L27/1104 ,  G09G3/3611 ,  G11C7/02 ,  G11C8/16 ,  G11C11/4125 ,  H01L27/11

    摘要： A dual port semiconductor memory device, including PMOS scan transistors, is provided. The dual port semiconductor memory device includes two PMOS transistors, two NMOS pull-down transistors, two NMOS pass transistors, and a PMOS scan transistor. The scan transistor being PMOS, noise margins can be improved. In addition, these seven transistors are arranged in two n-wells and 2 p-wells, while n-wells and p-wells are arranged in series and in alternating fashion. Therefore, the length of a memory cell along the minor axis of the memory cell is relatively short. This memory cell layout helps shorten the length of a bit line by arranging a pair of bitlines in parallel with well boundaries, i.e., in the direction of the short axis of the memory cell, and makes it possible to prevent crosstalk between a bitline and a complementary bitline by arranging conductive lines between the bitline and the complementary bitline.

    摘要翻译： 提供了包括PMOS扫描晶体管的双端口半导体存储器件。 双端口半导体存储器件包括两个PMOS晶体管，两个NMOS下拉晶体管，两个NMOS传输晶体管和PMOS扫描晶体管。 作为PMOS的扫描晶体管，可以提高噪声容限。 此外，这七个晶体管排列在两个n阱和2个p阱中，而n阱和p阱以串联和交替的方式排列。 因此，沿着存储单元的短轴的存储单元的长度相对较短。 该存储单元布局通过将一对位线与阱边界并排布置，即在存储单元的短轴方向上有助于缩短位线的长度，并且可以防止位线与位线之间的串扰 通过在位线和互补位线之间布置导线来补充位线。

    Cell structure of non-volatile memory device and method for fabricating the same
    3.
    发明授权
    Cell structure of non-volatile memory device and method for fabricating the same 失效

    公开(公告)号：US06995421B2

    公开(公告)日：2006-02-07

    申请号：US10621571

    申请日：2003-07-18

    申请人： Tae-Jung Lee ,  Byung-Sun Kim ,  Joon-Hyung Lee

    发明人： Tae-Jung Lee ,  Byung-Sun Kim ,  Joon-Hyung Lee

    IPC分类号： H01L29/788

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

    摘要： A cell structure of a non-volatile memory device, which uses a nitride layer as a floating gate spacer, includes a gate stack and a floating gate transistor formed over a semiconductor substrate. The gate stack includes a first portion of a floating gate, a control gate formed over the first portion of the floating gate, and a non-nitride spacer adjacent to sidewalls of the first portion of floating gate. The floating gate transistor includes a second portion of the floating gate, which substantially overlaps a source and/or drain formed in the substrate. The application of ultraviolet rays to the non-nitride spacer of a programmed cell can causes the second portion of the floating gate to discharge, thereby easily erasing the programmed cell.

    Method for fabricating cell structure of non-volatile memory device
    4.
    发明授权
    Method for fabricating cell structure of non-volatile memory device 失效
    非易失性存储器件单元结构的制造方法

    公开(公告)号：US07445992B2

    公开(公告)日：2008-11-04

    申请号：US11281471

    申请日：2005-11-18

    申请人： Tae-Jung Lee ,  Byung-Sun Kim ,  Joon-Hyung Lee

    发明人： Tae-Jung Lee ,  Byung-Sun Kim ,  Joon-Hyung Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

    摘要： A cell structure of a non-volatile memory device, which uses a nitride layer as a floating gate spacer, includes a gate stack and a floating gate transistor formed over a semiconductor substrate. The gate stack includes a first portion of a floating gate, a control gate formed over the first portion of the floating gate, and a non-nitride spacer adjacent to sidewalls of the first portion of floating gate. The floating gate transistor includes a second portion of the floating gate, which substantially overlaps a source and/or drain formed in the substrate. The application of ultraviolet rays to the non-nitride spacer of a programmed cell can causes the second portion of the floating gate to discharge, thereby easily erasing the programmed cell.

    摘要翻译： 使用氮化物层作为浮动栅极隔离物的非易失性存储器件的单元结构包括形成在半导体衬底上的栅极堆叠和浮置栅极晶体管。 栅极堆叠包括浮置栅极的第一部分，形成在浮置栅极的第一部分上的控制栅极以及与浮动栅极的第一部分的侧壁相邻的非氮化物间隔物。 浮栅晶体管包括浮置栅极的第二部分，其基本上与衬底中形成的源极和/或漏极重叠。 将紫外线施加到编程单元的非氮化物间隔物可能导致浮栅的第二部分放电，从而容易地擦除编程的单元。

    One-time programmable (OTP) memory cell and OTP memory device for multi-bit program
    5.
    发明授权
    One-time programmable (OTP) memory cell and OTP memory device for multi-bit program 有权
    一次性可编程（OTP）存储单元和用于多位程序的OTP存储器件

    公开(公告)号：US09524795B2

    公开(公告)日：2016-12-20

    申请号：US14847160

    申请日：2015-09-08

    申请人： Joon-Hyung Lee ,  Oh-Kyum Kwon

    发明人： Joon-Hyung Lee ,  Oh-Kyum Kwon

    IPC分类号： G11C17/16 ,  G11C17/18

    CPC分类号： G11C17/18 ,  G11C17/16

    摘要： A one-time programmable (OTP) memory device includes a memory cell array including a plurality of OTP memory cells, the plurality of OTP memory cells being connected to a plurality of bitlines, a plurality of voltage wordlines and a plurality of read wordlines, respectively; and a switching circuit configured to, in a program mode, detect program states of the plurality of OTP memory cells to block currents from flowing through the plurality of OTP memory cells from the voltage wordlines to the bitlines based on the detected program states.

    摘要翻译： 一次性可编程（OTP）存储器件包括包括多个OTP存储器单元的存储单元阵列，多个OTP存储器单元分别连接到多个位线，多个电压字线和多个读字线 ; 以及开关电路，被配置为在程序模式下，基于检测到的程序状态，检测多个OTP存储器单元的程序状态以阻止电流从电压字线流过多个OTP存储单元到位线。

    High-voltage semiconductor device and method of manufacturing the same
    9.
    发明申请
    High-voltage semiconductor device and method of manufacturing the same 审中-公开
    高压半导体器件及其制造方法

    公开(公告)号：US20060255369A1

    公开(公告)日：2006-11-16

    申请号：US11430580

    申请日：2006-05-09

    申请人： Yong-Chan Kim ,  Yong-Don Kim ,  Joon-Hyung Lee

    发明人： Yong-Chan Kim ,  Yong-Don Kim ,  Joon-Hyung Lee

    IPC分类号： H01L29/768

    CPC分类号： H01L27/0922 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/66606 ,  H01L29/7836

    摘要： A high-voltage semiconductor device and a method of manufacturing the high-voltage semiconductor device are provided. For example, with the above device and method drift regions having first depths are formed in a semiconductor substrate by doping first impurities. The drift regions are spaced apart from each other to define a channel region between the drift regions. Source/drain regions having second depths are formed at first portions of the drift regions by doping second impurities. Impurity accumulation regions having third depths are formed at second portions of the drift region adjacent to the source/drain regions by doping third impurities. A gate insulation layer pattern is formed on the semiconductor substrate to partially expose the source/drain regions. A gate conductive layer pattern is formed on a portion of the gate insulation layer pattern where the channel region is positioned. A buffer layer capable of preventing a rapid increase of a current is formed on the gate structure and the gate insulation layer pattern.

    摘要翻译： 提供一种高压半导体器件和制造该高压半导体器件的方法。 例如，通过掺杂第一杂质，在半导体衬底中形成具有第一深度的上述器件和方法漂移区。 漂移区域彼此间隔开以限定漂移区域之间的沟道区域。 通过掺杂第二杂质在漂移区的第一部分处形成具有第二深度的源/漏区。 通过掺杂第三杂质，在与源极/漏极区相邻的漂移区的第二部分处形成具有第三深度的杂质聚集区。 在半导体衬底上形成栅极绝缘层图案以部分地暴露源极/漏极区域。 栅极导电层图案形成在栅极绝缘层图案的其中定位沟道区域的部分上。 在栅极结构和栅极绝缘层图案上形成能够防止电流快速增加的缓冲层。