公开(公告)号：US20090055572A1

公开(公告)日：2009-02-26

申请号：US11843434

申请日：2007-08-22

申请人： Tahsin Askar ,  Philip E. Madrid

发明人： Tahsin Askar ,  Philip E. Madrid

IPC分类号： G06F12/00

CPC分类号： G06F13/1684

摘要： A DRAM controller may comprise two sub-controllers, each capable of handling a respective N-bit interface (e.g. 64-bit interface). Each sub-controller may also be configurable to be (2*N)-bit (e.g. 128-bit) capable with respect to control logic, for controlling a logical 128-bit data path. In ganged mode, each sub-controller may logically operate as if it were handling data in 128-bit chunks, (i.e. handling the entire 128-bit data path), while actual full bandwidth may be achieved by having one of the sub-controllers operate on commands and a first N-bit portion of each (2*N)-bit chunk of data, and having the other sub-controller operate on a “copy” of the commands with a corresponding remaining N-bit portion of each (2*N)-bit chunk of data. Once the BIOS has configured and initialized the two DRAM controllers to operate in ganged mode, the BIOS and all software may no longer need to be aware that two memory controllers are used to access a single (2*N)-bit wide channel.

摘要翻译： DRAM控制器可以包括两个子控制器，每个子控制器能够处理相应的N位接口（例如，64位接口）。 每个子控制器还可以被配置为相对于控制逻辑能够（2 * N）位（例如128位），用于控制逻辑128位数据路径。 在联动模式下，每个子控制器可以在逻辑上操作，就像处理128位块中的数据一样（即处理整个128位数据路径），而实际的全带宽可以通过使其中一个子控制器 对每个（2 * N）位数据块的命令和第一N位部分进行操作，并且使另一个子控制器对命令的“复制”与每个（2×N）位数据的相应的剩余N位部分进行操作 2 * N）位数据块。 一旦BIOS配置并初始化了两个DRAM控制器以联合模式运行，则BIOS和所有软件可能不再需要注意两个存储器控制器用于访问单个（2 * N）位宽通道。

公开(公告)号：US08607104B2

公开(公告)日：2013-12-10

申请号：US12972977

申请日：2010-12-20

申请人： Hanwoo Cho ,  Tahsin Askar ,  Philip E. Madrid ,  Guhan Krishnan ,  Brian W. Amick ,  Shawn Searles ,  Ryan J. Hensley

发明人： Hanwoo Cho ,  Tahsin Askar ,  Philip E. Madrid ,  Guhan Krishnan ,  Brian W. Amick ,  Shawn Searles ,  Ryan J. Hensley

IPC分类号： G06F11/00

CPC分类号： G11C29/1201 ,  G11C29/022

摘要： A memory loopback system and method including an address/command transmit source configured to transmit a command and associated address through an address/command path. A transmit data source is configured to transmit write data associated with the command through a write path. Test control logic is configured to generate gaps between successive commands. A loopback connection is configured to route the write data from the write path to a read path. A data comparator is configured to compare the data received via the read path to a receive data source and generate a data loopback status output. Pattern generation logic can be configured to generate a loopback strobe, the loopback strobe being coupled to the read path. The pattern generation logic may be configured to synthesize a read strobe based on the test control logic and to use the synthesized read strobe as the loopback strobe. The loopback connection may be configured to route the address/command data from the address/command path to an address/command comparator, the address/command comparator being configured to compare the address/command data to an address/command receive source and generate an address/command loopback status output.

摘要翻译： 一种存储器环回系统和方法，包括地址/命令发送源，其被配置为通过地址/命令路径发送命令和相关联的地址。 发送数据源被配置为通过写入路径发送与该命令相关联的写入数据。 测试控制逻辑被配置为在连续命令之间产生间隙。 配置环回连接将写入数据从写入路径路由到读取路径。 数据比较器被配置为将经由读取路径接收的数据与接收数据源进行比较，并生成数据环回状态输出。 模式生成逻辑可被配置为生成环回选通，环回选通被耦合到读取路径。 图案生成逻辑可以被配置为基于测试控制逻辑来合成读选通脉冲，并且使用合成的读选通作为环回选通。 环回连接可以被配置为将地址/命令数据从地址/命令路径路由到地址/命令比较器，地址/命令比较器被配置为将地址/命令数据与地址/命令接收源进行比较，并生成 地址/命令环回状态输出。

公开(公告)号：US09122648B2

公开(公告)日：2015-09-01

申请号：US11843428

申请日：2007-08-22

申请人： Tahsin Askar ,  Philip E. Madrid

发明人： Tahsin Askar ,  Philip E. Madrid

IPC分类号： G06F3/00 ,  G06F13/16

CPC分类号： G06F13/161

摘要： A method for throttling a bus, e.g. a memory bus, may be used to compensate for potential inaccuracy of feedback information received for monitored characteristics, e.g. temperature, reported by sensors configured in monitored devices, e.g. memory devices, accessed through the bus. For example, in case of a memory bus, a memory controller may be configured to throttle the memory bus in a way that maximizes system performance while ensuring that the memory devices keep operating within their thermal limits. Readings obtained from the memory, or from close proximity to the memory, may indicate whether the temperature of the memory has crossed over one or more designated trip points, and one or more algorithms may be executed to perform throttling according to the readings and based on fixed and dynamic throttling modes. The memory controller may infer temperature changes taking place in the memory devices when successive readings are indicating that the temperature of the memory device has remained over a given trip point. Based on these inferences, the memory controller may then change the manner in which the bus is throttled.

摘要翻译： 一种用于扼流总线的方法，例如 存储器总线可以用于补偿为监视特性而接收的反馈信息的潜在不准确性，例如， 温度由在被监控设备中配置的传感器报告。 存储设备，通过总线访问。 例如，在存储器总线的情况下，存储器控制器可以被配置为以使得系统性能最大化的方式来扼制存储器总线，同时确保存储器件在其热限制内保持工作。 从存储器或从靠近存储器获得的读取可以指示存储器的温度是否超过一个或多个指定的跳变点，并且可以执行一个或多个算法以根据读数执行调节，并且基于 固定和动态节流模式。 当连续读数指示存储器件的温度保持在给定跳变点以上时，存储器控制器可以推断在存储器件中发生的温度变化。 基于这些推论，存储器控制器然后可以改变总线被节流的方式。

公开(公告)号：US20120159271A1

公开(公告)日：2012-06-21

申请号：US12972977

申请日：2010-12-20

申请人： Hanwoo Cho ,  Tahsin Askar ,  Philip E. Madrid ,  Guhan Krishnan ,  Brian W. Amick ,  Shawn Searles ,  Ryan J. Hensley

发明人： Hanwoo Cho ,  Tahsin Askar ,  Philip E. Madrid ,  Guhan Krishnan ,  Brian W. Amick ,  Shawn Searles ,  Ryan J. Hensley

IPC分类号： G06F11/263

CPC分类号： G11C29/1201 ,  G11C29/022

摘要： A memory loopback system and method including an address/command transmit source configured to transmit a command and associated address through an address/command path. A transmit data source is configured to transmit write data associated with the command through a write path. Test control logic is configured to generate gaps between successive commands. A loopback connection is configured to route the write data from the write path to a read path. A data comparator is configured to compare the data received via the read path to a receive data source and generate a data loopback status output. Pattern generation logic can be configured to generate a loopback strobe, the loopback strobe being coupled to the read path. The pattern generation logic may be configured to synthesize a read strobe based on the test control logic and to use the synthesized read strobe as the loopback strobe. The loopback connection may be configured to route the address/command data from the address/command path to an address/command comparator, the address/command comparator being configured to compare the address/command data to an address/command receive source and generate an address/command loopback status output.

摘要翻译： 一种存储器环回系统和方法，包括地址/命令发送源，其被配置为通过地址/命令路径发送命令和相关联的地址。 发送数据源被配置为通过写入路径发送与该命令相关联的写入数据。 测试控制逻辑被配置为在连续命令之间产生间隙。 配置环回连接将写入数据从写入路径路由到读取路径。 数据比较器被配置为将经由读取路径接收的数据与接收数据源进行比较，并生成数据环回状态输出。 模式生成逻辑可被配置为生成环回选通，环回选通被耦合到读取路径。 图案生成逻辑可以被配置为基于测试控制逻辑来合成读选通脉冲，并且使用合成的读选通作为环回选通。 环回连接可以被配置为将地址/命令数据从地址/命令路径路由到地址/命令比较器，地址/命令比较器被配置为将地址/命令数据与地址/命令接收源进行比较，并生成 地址/命令环回状态输出。

公开(公告)号：US20090055570A1

公开(公告)日：2009-02-26

申请号：US11843443

申请日：2007-08-22

申请人： Philip E. Madrid ,  Tahsin Askar

发明人： Philip E. Madrid ,  Tahsin Askar

IPC分类号： G06F12/00

CPC分类号： G06F12/0215 ,  G06F13/161

摘要： A DRAM controller may be configured to re-order read/write requests to maximize the number of page hits and minimize the number of page conflicts and page misses. A three-level prediction algorithm may be performed to obtain auto-precharge prediction for each read/write request, without having to track every individual page. Instead, the DRAM controller may track the history of page activity for each bank of DRAM, and make a prediction to first order based history that is not bank based. The memory requests may be stored in a queue, a specified number at a time, and used to determine whether a page should be closed or left open following access to that page. If no future requests in the queue are to the given bank containing the page, recent bank history for that bank may be used to obtain a prediction whether the page should be closed or left open. If the page is not closed as a result of the determination and/or prediction, it may be left open and closed after it has remained idle a specified length of time following the last access to the page.

摘要翻译： DRAM控制器可以被配置为重新排序读/写请求以最大化页面命中的数量并且最小化页面冲突和页错过的次数。 可以执行三电平预测算法以获得每个读/写请求的自动预充电预测，而不必跟踪每个单独的页面。 相反，DRAM控制器可以跟踪每个DRAM行的页面活动的历史，并且对基于非银行的基于第一阶的历史进行预测。 存储器请求可以一次存储在一个队列中，一个指定的数字，并且用于确定在访问该页面之后页面是应该被关闭还是保持打开。 如果队列中未来的请求不包含该页面的给定银行，则该银行的最近银行历史记录可用于获取该页面是否应该被关闭或保持打开的预测。 如果作为确定和/或预测的结果没有关闭页面，则可以在最后访问页面之后指定的时间长度保持空闲之后将其打开并关闭。

公开(公告)号：US08006032B2

公开(公告)日：2011-08-23

申请号：US11843434

申请日：2007-08-22

申请人： Tahsin Askar ,  Philip E. Madrid

发明人： Tahsin Askar ,  Philip E. Madrid

IPC分类号： G06F12/00

CPC分类号： G06F13/1684

摘要： A dynamic random access memory (DRAM) controller may comprise two sub-controllers, each capable of handling a respective N-bit interface (e.g. 64-bit interface). Each sub-controller may also be configurable to be (2*N)-bit (e.g. 128-bit) capable with respect to control logic, for controlling a logical 128-bit data path. In ganged mode, each sub-controller may logically operate as if it were handling data in 128-bit chunks, (i.e. handling the entire 128-bit data path), while actual full bandwidth may be achieved by having one of the sub-controllers operate on commands and a first N-bit portion of each (2*N)-bit chunk of data, and having the other sub-controller operate on a “copy” of the commands with a corresponding remaining N-bit portion of each (2*N)-bit chunk of data. Once the basic input/output system (BIOS) has configured and initialized the two DRAM controllers to operate in ganged mode, the BIOS and all software may no longer need to be aware that two memory controllers are used to access a single (2*N)-bit wide channel.

摘要翻译： 动态随机存取存储器（DRAM）控制器可以包括两个子控制器，每个子控制器能够处理相应的N位接口（例如，64位接口）。 每个子控制器还可以被配置为相对于控制逻辑能够（2 * N）位（例如128位），用于控制逻辑128位数据路径。 在联动模式下，每个子控制器可以在逻辑上操作，就像处理128位块中的数据一样（即处理整个128位数据路径），而实际的全带宽可以通过使其中一个子控制器 对每个（2 * N）位数据块的命令和第一N位部分进行操作，并且使另一个子控制器对命令的“复制”与每个（2×N）位数据的相应的剩余N位部分进行操作 2 * N）位数据块。 一旦基本输入/输出系统（BIOS）配置并初始化了两个DRAM控制器以组合模式运行，BIOS和所有软件可能不再需要注意两个存储器控制器用于访问单个（2 * N ）位宽通道。

公开(公告)号：US07761656B2

公开(公告)日：2010-07-20

申请号：US11843443

申请日：2007-08-22

申请人： Philip E. Madrid ,  Tahsin Askar

发明人： Philip E. Madrid ,  Tahsin Askar

IPC分类号： G06F12/00

CPC分类号： G06F12/0215 ,  G06F13/161

摘要： A DRAM controller may be configured to re-order read/write requests to maximize the number of page hits and minimize the number of page conflicts and page misses. A three-level prediction algorithm may be performed to obtain auto-precharge prediction for each read/write request, without having to track every individual page. Instead, the DRAM controller may track the history of page activity for each bank of DRAM, and make a prediction to first order based history that is not bank based. The memory requests may be stored in a queue, a specified number at a time, and used to determine whether a page should be closed or left open following access to that page. If no future requests in the queue are to the given bank containing the page, recent bank history for that bank may be used to obtain a prediction whether the page should be closed or left open. If the page is not closed as a result of the determination and/or prediction, it may be left open and closed after it has remained idle a specified length of time following the last access to the page.

摘要翻译： DRAM控制器可以被配置为重新排序读/写请求以最大化页面命中的数量并且最小化页面冲突和页错过的次数。 可以执行三电平预测算法以获得每个读/写请求的自动预充电预测，而不必跟踪每个单独的页面。 相反，DRAM控制器可以跟踪每个DRAM行的页面活动的历史，并且对基于非银行的基于第一阶的历史进行预测。 存储器请求可以一次存储在一个队列中，一个指定的数字，并且用于确定在访问该页面之后页面是应该被关闭还是保持打开。 如果队列中未来的请求不包含该页面的给定银行，则可能会使用该银行的最近银行历史记录来获取该页面是关闭还是打开的预测。 如果作为确定和/或预测的结果没有关闭页面，则可以在最后访问页面之后指定的时间长度保持空闲之后将其打开并关闭。

公开(公告)号：US20090052266A1

公开(公告)日：2009-02-26

申请号：US11843428

申请日：2007-08-22

申请人： Tahsin Askar ,  Philip E. Madrid

发明人： Tahsin Askar ,  Philip E. Madrid

IPC分类号： G11C7/04

CPC分类号： G06F13/161

摘要： A method for throttling a bus, e.g. a memory bus, may be used to compensate for potential inaccuracy of feedback information received for monitored characteristics, e.g. temperature, reported by sensors configured in monitored devices, e.g. memory devices, accessed through the bus. For example, in case of a memory bus, a memory controller may be configured to throttle the memory bus in a way that maximizes system performance while ensuring that the memory devices keep operating within their thermal limits. Readings obtained from the memory, or from close proximity to the memory, may indicate whether the temperature of the memory has crossed over one or more designated trip points, and one or more algorithms may be executed to perform throttling according to the readings and based on fixed and dynamic throttling modes. The memory controller may infer temperature changes taking place in the memory devices when successive readings are indicating that the temperature of the memory device has remained over a given trip point. Based on these inferences, the memory controller may then change the manner in which the bus is throttled.

摘要翻译： 一种用于扼流总线的方法，例如 存储器总线可以用于补偿为监视特性而接收的反馈信息的潜在不准确性，例如， 温度由在被监控设备中配置的传感器报告。 存储设备，通过总线访问。 例如，在存储器总线的情况下，存储器控制器可以被配置为以使得系统性能最大化的方式来扼制存储器总线，同时确保存储器件在其热限制内保持工作。 从存储器或从靠近存储器获得的读取可以指示存储器的温度是否超过一个或多个指定的跳变点，并且可以执行一个或多个算法以根据读数执行调节，并且基于 固定和动态节流模式。 当连续读数指示存储器件的温度保持在给定跳变点以上时，存储器控制器可以推断在存储器件中发生的温度变化。 基于这些推论，存储器控制器然后可以改变总线被节流的方式。

公开(公告)号：US06834314B1

公开(公告)日：2004-12-21

申请号：US10093055

申请日：2002-03-07

申请人： Tahsin Askar

发明人： Tahsin Askar

IPC分类号： G06F1300

CPC分类号： G06F13/128

摘要： An apparatus for reordering packet transactions within a peripheral interface circuit. The apparatus includes a source tagging unit and a control unit. The source tagging unit may be configured to generate a plurality of tag values each corresponding to one of a plurality of packet commands. The control unit may include a first storage unit including a first plurality of locations and a second storage unit including a second plurality of locations. Each of the locations corresponds to one of the plurality of tag values. Each of the first plurality of locations may provide an indication of whether a given tag value corresponds to a first packet command in a given data stream. A first given location of the second plurality of locations corresponds to the tag value indicated by the first storage unit and stores a tag value of a second packet command in the given data stream.

摘要翻译： 一种用于在外围接口电路内重新排序分组事务的装置。 该装置包括源标签单元和控制单元。 源标签单元可以被配置为生成与多个分组命令之一对应的多个标签值。 控制单元可以包括包括第一多个位置的第一存储单元和包括第二多个位置的第二存储单元。 每个位置对应于多个标签值之一。 第一多个位置中的每一个可以提供给定标签值是否对应于给定数据流中的第一分组命令的指示。 第二多个位置的第一给定位置对应于由第一存储单元指示的标签值，并将给定数据流中的第二包命令的标签值存储。

公开(公告)号：US06883045B1

公开(公告)日：2005-04-19

申请号：US10093124

申请日：2002-03-07

申请人： Tahsin Askar ,  Eric G. Chambers

发明人： Tahsin Askar ,  Eric G. Chambers

IPC分类号： G06F13/12 ,  G06F13/00

CPC分类号： G06F13/128

摘要： An apparatus for reordering graphics responses in a peripheral interface circuit for an I/O node of a computer system. The apparatus includes a data buffer and a control unit. The data buffer includes a first plurality of storage locations each corresponding to one of a plurality of tag values. The data buffer may receive a plurality of data packets associated with the graphics transactions. The data buffer may also store the data packets in the storage locations according to tag values. The control unit includes a storage unit having a second plurality of locations. Each of the locations in the storage unit corresponds to one of the tag values and may provide an indication of whether a given data packet has been stored in the data buffer. The control unit may further determine an order in which the plurality of data packets is read from the data buffer.

摘要翻译： 一种用于在计算机系统的I / O节点的外围接口电路中重新排序图形响应的装置。 该装置包括数据缓冲器和控制单元。 数据缓冲器包括每个对应于多个标签值之一的第一多个存储位置。 数据缓冲器可以接收与图形事务相关联的多个数据分组。 数据缓冲器还可以根据标签值将数据包存储在存储位置。 控制单元包括具有第二多个位置的存储单元。 存储单元中的每个位置对应于标签值之一，并且可以提供给定数据分组是否已经存储在数据缓冲器中的指示。 控制单元还可以从数据缓冲器中确定读取多个数据分组的顺序。