公开(公告)号：US08607104B2

公开(公告)日：2013-12-10

申请号：US12972977

申请日：2010-12-20

申请人： Hanwoo Cho ,  Tahsin Askar ,  Philip E. Madrid ,  Guhan Krishnan ,  Brian W. Amick ,  Shawn Searles ,  Ryan J. Hensley

发明人： Hanwoo Cho ,  Tahsin Askar ,  Philip E. Madrid ,  Guhan Krishnan ,  Brian W. Amick ,  Shawn Searles ,  Ryan J. Hensley

IPC分类号： G06F11/00

CPC分类号： G11C29/1201 ,  G11C29/022

摘要： A memory loopback system and method including an address/command transmit source configured to transmit a command and associated address through an address/command path. A transmit data source is configured to transmit write data associated with the command through a write path. Test control logic is configured to generate gaps between successive commands. A loopback connection is configured to route the write data from the write path to a read path. A data comparator is configured to compare the data received via the read path to a receive data source and generate a data loopback status output. Pattern generation logic can be configured to generate a loopback strobe, the loopback strobe being coupled to the read path. The pattern generation logic may be configured to synthesize a read strobe based on the test control logic and to use the synthesized read strobe as the loopback strobe. The loopback connection may be configured to route the address/command data from the address/command path to an address/command comparator, the address/command comparator being configured to compare the address/command data to an address/command receive source and generate an address/command loopback status output.

摘要翻译： 一种存储器环回系统和方法，包括地址/命令发送源，其被配置为通过地址/命令路径发送命令和相关联的地址。 发送数据源被配置为通过写入路径发送与该命令相关联的写入数据。 测试控制逻辑被配置为在连续命令之间产生间隙。 配置环回连接将写入数据从写入路径路由到读取路径。 数据比较器被配置为将经由读取路径接收的数据与接收数据源进行比较，并生成数据环回状态输出。 模式生成逻辑可被配置为生成环回选通，环回选通被耦合到读取路径。 图案生成逻辑可以被配置为基于测试控制逻辑来合成读选通脉冲，并且使用合成的读选通作为环回选通。 环回连接可以被配置为将地址/命令数据从地址/命令路径路由到地址/命令比较器，地址/命令比较器被配置为将地址/命令数据与地址/命令接收源进行比较，并生成 地址/命令环回状态输出。

公开(公告)号：US20120159271A1

公开(公告)日：2012-06-21

申请号：US12972977

申请日：2010-12-20

申请人： Hanwoo Cho ,  Tahsin Askar ,  Philip E. Madrid ,  Guhan Krishnan ,  Brian W. Amick ,  Shawn Searles ,  Ryan J. Hensley

发明人： Hanwoo Cho ,  Tahsin Askar ,  Philip E. Madrid ,  Guhan Krishnan ,  Brian W. Amick ,  Shawn Searles ,  Ryan J. Hensley

IPC分类号： G06F11/263

CPC分类号： G11C29/1201 ,  G11C29/022

摘要： A memory loopback system and method including an address/command transmit source configured to transmit a command and associated address through an address/command path. A transmit data source is configured to transmit write data associated with the command through a write path. Test control logic is configured to generate gaps between successive commands. A loopback connection is configured to route the write data from the write path to a read path. A data comparator is configured to compare the data received via the read path to a receive data source and generate a data loopback status output. Pattern generation logic can be configured to generate a loopback strobe, the loopback strobe being coupled to the read path. The pattern generation logic may be configured to synthesize a read strobe based on the test control logic and to use the synthesized read strobe as the loopback strobe. The loopback connection may be configured to route the address/command data from the address/command path to an address/command comparator, the address/command comparator being configured to compare the address/command data to an address/command receive source and generate an address/command loopback status output.

摘要翻译： 一种存储器环回系统和方法，包括地址/命令发送源，其被配置为通过地址/命令路径发送命令和相关联的地址。 发送数据源被配置为通过写入路径发送与该命令相关联的写入数据。 测试控制逻辑被配置为在连续命令之间产生间隙。 配置环回连接将写入数据从写入路径路由到读取路径。 数据比较器被配置为将经由读取路径接收的数据与接收数据源进行比较，并生成数据环回状态输出。 模式生成逻辑可被配置为生成环回选通，环回选通被耦合到读取路径。 图案生成逻辑可以被配置为基于测试控制逻辑来合成读选通脉冲，并且使用合成的读选通作为环回选通。 环回连接可以被配置为将地址/命令数据从地址/命令路径路由到地址/命令比较器，地址/命令比较器被配置为将地址/命令数据与地址/命令接收源进行比较，并生成 地址/命令环回状态输出。

公开(公告)号：US08880831B2

公开(公告)日：2014-11-04

申请号：US13106285

申请日：2011-05-12

申请人： Guhan Krishnan ,  Jonathan M. Owen ,  Brian Amick ,  Hanwoo Cho

发明人： Guhan Krishnan ,  Jonathan M. Owen ,  Brian Amick ,  Hanwoo Cho

IPC分类号： G06F13/16

CPC分类号： G06F13/1663 ,  G06F13/1689

摘要： A method and apparatus for training read latency of a memory are disclosed. A memory controller includes a command FIFO configured to convey commands to a memory, a data queue coupled to receive data from the memory, and a register configured to provide a value indicative of a number of cycles of a first clock signal after which data is valid. During a startup routine, the memory controller is configured to compare data received by the data queue to a known data pattern after a specified number of cycles of the first clock signal have elapsed. The memory controller is further to configured to decrement the first value and repeat conveying and comparing if the data received matches the data pattern. If the received data does not match the data pattern for any attempted read of the memory, the memory controller is configured to program a second value into the register.

摘要翻译： 公开了一种用于训练存储器的读延迟的方法和装置。 存储器控制器包括被配置为将命令传送到存储器的命令FIFO，耦合以从存储器接收数据的数据队列，以及配置为提供表示数据有效的第一时钟信号的周期数的寄存器 。 在启动程序期间，存储器控制器被配置为在经过第一时钟信号的指定数量的周期之后，将由数据队列接收的数据与已知数据模式进行比较。 存储器控制器还被配置为递减第一值，并且如果接收的数据与数据模式匹配，则重复传送和比较。 如果接收的数据与存储器的任何尝试读取的数据模式不匹配，则存储器控制器被配置为将第二值编程到寄存器中。

公开(公告)号：US20120290800A1

公开(公告)日：2012-11-15

申请号：US13106285

申请日：2011-05-12

申请人： Guhan Krishnan ,  Jonathan M. Owen ,  Brian Amick ,  Hanwoo Cho

发明人： Guhan Krishnan ,  Jonathan M. Owen ,  Brian Amick ,  Hanwoo Cho

IPC分类号： G06F12/02

CPC分类号： G06F13/1663 ,  G06F13/1689

摘要： A method and apparatus for training read latency of a memory are disclosed. A memory controller includes a command FIFO configured to convey commands to a memory, a data queue coupled to receive data from the memory, and a register configured to provide a value indicative of a number of cycles of a first clock signal after which data is valid. During a startup routine, the memory controller is configured to compare data received by the data queue to a known data pattern after a specified number of cycles of the first clock signal have elapsed. The memory controller is further to configured to decrement the first value and repeat conveying and comparing if the data received matches the data pattern. If the received data does not match the data pattern for any attempted read of the memory, the memory controller is configured to program a second value into the register.

摘要翻译： 公开了一种用于训练存储器的读延迟的方法和装置。 存储器控制器包括被配置为将命令传送到存储器的命令FIFO，耦合以从存储器接收数据的数据队列，以及配置为提供表示数据有效的第一时钟信号的周期数的寄存器 。 在启动程序期间，存储器控制器被配置为在经过第一时钟信号的指定数量的周期之后，将由数据队列接收的数据与已知数据模式进行比较。 存储器控制器还被配置为递减第一值，并且如果接收的数据与数据模式匹配，则重复传送和比较。 如果接收的数据与存储器的任何尝试读取的数据模式不匹配，则存储器控制器被配置为将第二值编程到寄存器中。

公开(公告)号：US08924758B2

公开(公告)日：2014-12-30

申请号：US13360012

申请日：2012-01-27

申请人： Maurice B. Steinman ,  Alexander J. Branover ,  Guhan Krishnan

发明人： Maurice B. Steinman ,  Alexander J. Branover ,  Guhan Krishnan

IPC分类号： G06F1/32

CPC分类号： G06F1/3243 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/14 ,  Y02D10/172 ,  Y02D10/22

摘要： A system and method for efficient management of resources within a semiconductor chip for an optimal combination of power reduction and high performance. An intergrated circuit, such as a system on a chip (SOC), includes at least two processing units. The second processing unit includes a cache. The SOC includes a power management unit (PMU) that determines whether a first activity level for the first processing unit is above a first threshold and a second activity level for the second processing unit is below a second threshold. If this condition is true, then the PMU places a limit on a highest power-performance state (P-state) used by the second processing unit. The PMU sends an indication to flush the at least one cache within the second processing unit. The PMU changes a P-state used by the first processing unit to a higher performance P-state.

摘要翻译： 一种用于有效管理半导体芯片内的资源以实现功率降低和高性能的最佳组合的系统和方法。 诸如片上系统（SOC）的集成电路包括至少两个处理单元。 第二处理单元包括高速缓存。 SOC包括功率管理单元（PMU），其确定第一处理单元的第一活动级别是否高于第一阈值，并且第二处理单元的第二活动级别低于第二阈值。 如果该条件为真，则PMU对第二处理单元使用的最高功率状态（P状态）设置限制。 PMU发送指示以刷新第二处理单元内的至少一个高速缓存。 PMU将第一处理单元使用的P状态改变为更高性能的P状态。

公开(公告)号：US08862909B2

公开(公告)日：2014-10-14

申请号：US13310231

申请日：2011-12-02

申请人： Alexander J. Branover ,  Madhu Saravana Sibi Govindan ,  Guhan Krishnan ,  Hemant R. Mohapatra ,  Andrew W. Lueck

发明人： Alexander J. Branover ,  Madhu Saravana Sibi Govindan ,  Guhan Krishnan ,  Hemant R. Mohapatra ,  Andrew W. Lueck

IPC分类号： G06F1/00 ,  G06F1/32 ,  G06F1/26

CPC分类号： G06F1/32 ,  G06F1/00 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126

摘要： A system and method for efficient management of operating modes within an IC for optimal power and performance targets. On a same die, an SOC includes one or more processing units and a input/output (I/O) controller (IOC). The multiple interfaces within the IOC manage packets and messages according multiple different protocols. The IOC maintains an activity level for each one of the multiple interfaces. This activity level may be based at least on a respective number of transactions executed by a corresponding one of the multiple interfaces. The IOC determines a power estimate for itself based on at least the activity levels. In response to detecting a difference between the power estimate and an assigned I/O power limit for the IOC, a power manager adjusts at least respective power limits for the one or more processing units based on at least the difference.

摘要翻译： 一种用于高效管理IC内的运行模式以实现最佳功率和性能目标的系统和方法。 在相同的芯片上，SOC包括一个或多个处理单元和输入/输出（I / O）控制器（IOC）。 IOC中的多个接口根据多种不同的协议管理数据包和消息。 IOC维护多个接口中的每一个的活动级别。 该活动级别可以至少基于由多个接口中的相应一个执行的事务的相应数量。 至少基于活动水平，国际奥委会决定自己的能力估计。 响应于检测到功率估计与IOC的分配的I / O功率限制之间的差异，功率管理器至少基于差异来调整至少相应的一个或多个处理单元的功率限制。

公开(公告)号：US20130151869A1

公开(公告)日：2013-06-13

申请号：US13360012

申请日：2012-01-27

申请人： Maurice B. Steinman ,  Alexander J. Branover ,  Guhan Krishnan

发明人： Maurice B. Steinman ,  Alexander J. Branover ,  Guhan Krishnan

IPC分类号： G06F1/26

CPC分类号： G06F1/3243 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/14 ,  Y02D10/172 ,  Y02D10/22

摘要： A system and method for efficient management of resources within a semiconductor chip for an optimal combination of power reduction and high performance. An intergrated circuit, such as a system on a chip (SOC), includes at least two processing units. The second processing unit includes a cache. The SOC includes a power management unit (PMU) that determines whether a first activity level for the first processing unit is above a first threshold and a second activity level for the second processing unit is below a second threshold. If this condition is true, then the PMU places a limit on a highest power-performance state (P-state) used by the second processing unit. The PMU sends an indication to flush the at least one cache within the second processing unit. The PMU changes a P-state used by the first processing unit to a higher performance P-state.

摘要翻译： 一种用于有效管理半导体芯片内的资源以实现功率降低和高性能的最佳组合的系统和方法。 诸如片上系统（SOC）的集成电路包括至少两个处理单元。 第二处理单元包括高速缓存。 SOC包括功率管理单元（PMU），其确定第一处理单元的第一活动级别是否高于第一阈值，并且第二处理单元的第二活动级别低于第二阈值。 如果该条件为真，则PMU对第二处理单元使用的最高功率状态（P状态）设置限制。 PMU发送指示以刷新第二处理单元内的至少一个高速缓存。 PMU将第一处理单元使用的P状态改变为更高性能的P状态。

公开(公告)号：US08341344B2

公开(公告)日：2012-12-25

申请号：US11859044

申请日：2007-09-21

申请人： Guhan Krishnan ,  John Kalamatianos

发明人： Guhan Krishnan ,  John Kalamatianos

IPC分类号： G06F12/00 ,  G06F9/46

CPC分类号： G06F9/5016

摘要： A technique of accessing a resource includes receiving, at a master scheduler, resource access requests. The resource access requests are translated into respective slave state machine work orders that each include one or more respective commands. The respective commands are assigned, for execution, to command streams associated with respective slave state machines. The respective commands are then executed responsive to the respective slave state machines.

摘要翻译： 访问资源的技术包括在主调度器处接收资源访问请求。 资源访问请求被转换成各自的从状态机工作单，其各自包括一个或多个相应的命令。 相应的命令被分配用于执行以命令与相应从属状态机相关联的流。 然后响应于相应的从状态机执行各自的命令。

公开(公告)号：US08589629B2

公开(公告)日：2013-11-19

申请号：US12413124

申请日：2009-03-27

申请人： Jonathan Owen ,  Guhan Krishnan ,  Carl D. Dietz ,  Douglas Richard Beard ,  William K. Lewchuk ,  Alexander Branover

发明人： Jonathan Owen ,  Guhan Krishnan ,  Carl D. Dietz ,  Douglas Richard Beard ,  William K. Lewchuk ,  Alexander Branover

IPC分类号： G06F12/00

CPC分类号： G06F12/126 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/0888

摘要： A system and method for data allocation in a shared cache memory of a computing system are contemplated. Each cache way of a shared set-associative cache is accessible to multiple sources, such as one or more processor cores, a graphics processing unit (GPU), an input/output (I/O) device, or multiple different software threads. A shared cache controller enables or disables access separately to each of the cache ways based upon the corresponding source of a received memory request. One or more configuration and status registers (CSRs) store encoded values used to alter accessibility to each of the shared cache ways. The control of the accessibility of the shared cache ways via altering stored values in the CSRs may be used to create a pseudo-RAM structure within the shared cache and to progressively reduce the size of the shared cache during a power-down sequence while the shared cache continues operation.

摘要翻译： 预期在计算系统的共享高速缓冲存储器中进行数据分配的系统和方法。 共享组相关高速缓存的每个缓存方式可以被多个源访问，诸如一个或多个处理器核，图形处理单元（GPU），输入/输出（I / O）设备或多个不同的软件线程。 共享高速缓存控制器基于所接收的存储器请求的相应源，启用或禁用对每个高速缓存路径的访问。 一个或多个配置和状态寄存器（CSR）存储用于改变对每个共享缓存方式的可访问性的编码值。 可以通过改变CSR中的存储值来控制共享缓存方式的可访问性，以在共享高速缓存内创建伪RAM结构，并且在断电序列期间逐渐减小共享高速缓存的大小，而共享高速缓存共享 缓存继续运行。

公开(公告)号：US08516305B2

公开(公告)日：2013-08-20

申请号：US12873913

申请日：2010-09-01

申请人： Sebastien Nussbaum ,  Guhan Krishnan

发明人： Sebastien Nussbaum ,  Guhan Krishnan

IPC分类号： G06F11/00

CPC分类号： G06F11/27 ,  G01R31/30

摘要： Dynamic power test slave (DPTS) modules are placed at selected locations of a data processing device to provide data to a logic module of the device at a high rate during testing of the device. The DPTS module intercepts data requests targeted to another logic module and the DPTS instead provides the requested data, thus simulating data transfer by the target logic module. The simulated data transfers can provide for transitions at the data processing device from a relatively high power state to a relatively low power state. Accordingly, the DPTS modules allow for simulation of expected normal operating conditions during testing of the data processing device.

摘要翻译： 动态功率测试从站（DPTS）模块放置在数据处理设备的选定位置，以在设备测试期间以高速率向设备的逻辑模块提供数据。 DPTS模块拦截针对另一个逻辑模块的数据请求，DPTS代替提供所请求的数据，从而模拟目标逻辑模块的数据传输。 模拟数据传输可以提供数据处理设备从相对较高功率状态到相对低功率状态的转变。 因此，DPTS模块允许在测试数据处理设备期间模拟期望的正常操作条件。