公开(公告)号：US20240162349A1

公开(公告)日：2024-05-16

申请号：US18421681

申请日：2024-01-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Po-Cheng Chen ,  Kuo-Chan Huang ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Chien-Hao Chen

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545

Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

公开(公告)号：US20220238715A1

公开(公告)日：2022-07-28

申请号：US17658708

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Po-Cheng Chen ,  Kuo-Chan Huang ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Chien-Hao Chen

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/40 ,  H01L29/49

Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

公开(公告)号：US12183629B2

公开(公告)日：2024-12-31

申请号：US17813806

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Po-Cheng Chen ,  Kuo-Chan Huang ,  Pin-Hsuan Yeh ,  Wei-Chin Lee ,  Hsien-Ming Lee ,  Chien-Hao Chen ,  Chi On Chui

IPC: H01L21/768 ,  H01L29/423 ,  H01L29/78

Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.

公开(公告)号：US20240387257A1

公开(公告)日：2024-11-21

申请号：US18788514

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Po-Cheng Chen ,  Kuo-Chan Huang ,  Pin-Hsuan Yeh ,  Wei-Chin Lee ,  Hsien-Ming Lee ,  Chien-Hao Chen ,  Chi On Chui

IPC: H01L21/768 ,  H01L29/423 ,  H01L29/78

Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.

公开(公告)号：US11916146B2

公开(公告)日：2024-02-27

申请号：US17658708

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Po-Cheng Chen ,  Kuo-Chan Huang ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Chien-Hao Chen

IPC: H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7851 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545

Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

公开(公告)号：US11302818B2

公开(公告)日：2022-04-12

申请号：US16571879

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Po-Cheng Chen ,  Kuo-Chan Huang ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Chien-Hao Chen

IPC: H01L29/423 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/40 ,  H01L29/49

Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

公开(公告)号：US20210242081A1

公开(公告)日：2021-08-05

申请号：US16884837

申请日：2020-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Po-Cheng Chen ,  Kuo-Chan Huang ,  Pin-Hsuan Yeh ,  Wei-Chin Lee ,  Hsien-Ming Lee ,  Chien-Hao Chen ,  Chi On Chui

IPC: H01L21/768 ,  H01L29/423 ,  H01L29/78

Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.

公开(公告)号：US11532509B2

公开(公告)日：2022-12-20

申请号：US16884837

申请日：2020-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Po-Cheng Chen ,  Kuo-Chan Huang ,  Pin-Hsuan Yeh ,  Wei-Chin Lee ,  Hsien-Ming Lee ,  Chien-Hao Chen ,  Chi On Chui

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/423

Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.

公开(公告)号：US20220367261A1

公开(公告)日：2022-11-17

申请号：US17813806

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing CO., Ltd.

Inventor： Chung-Chiang Wu ,  Po-Cheng Chen ,  Kuo-Chan Huang ,  Pin-Hsuan Yeh ,  Wei-Chin Lee ,  Hsien-Ming Lee ,  Chien-Hao Chen ,  Chi On Chui

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/423

Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.

公开(公告)号：US20210083118A1

公开(公告)日：2021-03-18

申请号：US16571879

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Po-Cheng Chen ,  Kuo-Chan Huang ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Chien-Hao Chen

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/40 ,  H01L21/8234

Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.