公开(公告)号：US11652054B2

公开(公告)日：2023-05-16

申请号：US17236234

申请日：2021-04-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Chieh Yao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC: H01L23/535 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76895

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a dielectric on wire structure is arranged directly over the interconnect wire. Outer sidewalls of the dielectric on wire structure are surrounded by the first interconnect dielectric layer. The integrated chip further includes a second interconnect dielectric layer arranged over the first interconnect dielectric layer, and an interconnect via that extends through the second interconnect dielectric layer and the dielectric on wire structure to contact the interconnect wire.

公开(公告)号：US20140084479A1

公开(公告)日：2014-03-27

申请号：US13628346

申请日：2012-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Chieh Yao ,  Cheng-Hsiung Tsai ,  Chung-Ju Lee ,  Hsiang-Huan Lee

IPC: H01L23/00 ,  H01L21/02

CPC classification number: H01L23/562 ,  H01L21/02263 ,  H01L21/76837 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor device includes depositing a metal spacer over a core supported by a first extremely low-k dielectric layer having metal contacts embedded therein, etching away an upper portion of the metal spacer to expose the core between remaining lower portions of the metal spacer, removing the core from between the remaining lower portions of the metal spacer, and depositing a second extremely low-k dielectric layer over the remaining lower portions of the metal spacer.

Abstract translation: 一种形成半导体器件的方法包括：将金属间隔物沉积在由第一极低k电介质层支撑的芯上，所述第一极低k电介质层嵌入其中，蚀刻掉金属间隔物的上部以暴露所述金属间隔的剩余下部之间的芯 金属间隔件，从金属间隔件的其余下部之间移除芯，并且在金属间隔物的剩余下部上沉积第二极低k电介质层。

公开(公告)号：US20220013403A1

公开(公告)日：2022-01-13

申请号：US16923424

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsi-Wen Tien ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Shau-Lin Shue ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: The present disclosure relates to an integrated chip. The integrated chip comprises a dielectric layer over a substrate. A first metal feature is over the dielectric layer. A second metal feature is over the dielectric layer and is laterally adjacent to the first metal feature. A first dielectric liner segment extends laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer. The first dielectric liner segment extends continuously from along the upper surface of the dielectric layer, to along a sidewall of the first metal feature that faces the second metal feature, and to along a sidewall of the second metal feature that faces the first metal feature. A first cavity is laterally between sidewalls of the first dielectric liner segment and is above an upper surface of the first dielectric liner segment.

公开(公告)号：US11139236B2

公开(公告)日：2021-10-05

申请号：US16547750

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsi-Wen Tien ,  Wei-Hao Liao ,  Pin-Ren Dai ,  Hsin-Chieh Yao ,  Chih Wei Lu ,  Chung-Ju Lee

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/311

Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a metal feature in a first dielectric layer, an etch stop layer (ESL) over the metal feature, a second dielectric layer over the ESL, a third dielectric layer over the second dielectric layer, a patterned hard mask having a trench. The method further includes forming a via opening through the trench in the patterned hard mask, the second dielectric layer, the third dielectric layer, and the ESL to expose the metal feature, depositing a metal layer in the trench and the via opening to form a metal line and a metal contact via, respectively, and over the workpiece, removing the patterned hard mask between the metal line and the metal contact via, and depositing a fourth dielectric layer between the metal line and the metal contact via.

公开(公告)号：US20210057334A1

公开(公告)日：2021-02-25

申请号：US16547750

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsi-Wen Tien ,  Wei-Hao Liao ,  Pin-Ren Dai ,  Hsin-Chieh Yao ,  Chih Wei Lu ,  Chung-Ju Lee

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/311

Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a metal feature in a first dielectric layer, an etch stop layer (ESL) over the metal feature, a second dielectric layer over the ESL, a third dielectric layer over the second dielectric layer, a patterned hard mask having a trench. The method further includes forming a via opening through the trench in the patterned hard mask, the second dielectric layer, the third dielectric layer, and the ESL to expose the metal feature, depositing a metal layer in the trench and the via opening to form a metal line and a metal contact via, respectively, and over the workpiece, removing the patterned hard mask between the metal line and the metal contact via, and depositing a fourth dielectric layer between the metal line and the metal contact via.

公开(公告)号：US20220344264A1

公开(公告)日：2022-10-27

申请号：US17236234

申请日：2021-04-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Chieh Yao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC: H01L23/535 ,  H01L21/768

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a dielectric on wire structure is arranged directly over the interconnect wire. Outer sidewalls of the dielectric on wire structure are surrounded by the first interconnect dielectric layer. The integrated chip further includes a second interconnect dielectric layer arranged over the first interconnect dielectric layer, and an interconnect via that extends through the second interconnect dielectric layer and the dielectric on wire structure to contact the interconnect wire.

公开(公告)号：US11482447B2

公开(公告)日：2022-10-25

申请号：US16923424

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsi-Wen Tien ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Shau-Lin Shue ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

Abstract: The present disclosure relates to an integrated chip. The integrated chip comprises a dielectric layer over a substrate. A first metal feature is over the dielectric layer. A second metal feature is over the dielectric layer and is laterally adjacent to the first metal feature. A first dielectric liner segment extends laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer. The first dielectric liner segment extends continuously from along the upper surface of the dielectric layer, to along a sidewall of the first metal feature that faces the second metal feature, and to along a sidewall of the second metal feature that faces the first metal feature. A first cavity is laterally between sidewalls of the first dielectric liner segment and is above an upper surface of the first dielectric liner segment.

公开(公告)号：US11362030B2

公开(公告)日：2022-06-14

申请号：US16887475

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Teng Dai ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Hsi-Wen Tien ,  Wei-Hao Liao

IPC: H01L21/00 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

Abstract: Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) layer overlying a substrate. A lower conductive via is disposed within the first ILD layer. A plurality of conductive wires overlie the first ILD layer. A second ILD layer is disposed laterally between the conductive wires, where the second ILD layer comprises a first material. A sidewall spacer structure is disposed between the second ILD layer and the plurality of conductive wires. The sidewall spacer structure continuously extends along opposing sidewalls of each conductive wire. A top surface of the sidewall spacer structure is vertically above a top surface of the plurality of conductive wires, and the sidewall spacer structure comprises a second material different from the first material.

公开(公告)号：US11488926B2

公开(公告)日：2022-11-01

申请号：US16898670

申请日：2020-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Chieh Yao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC: H01L23/00 ,  H01L21/768

Abstract: The present disclosure relates to a semiconductor structure including an interconnect structure disposed over a semiconductor substrate. A lower metal line is disposed at a first height over the semiconductor substrate and extends through a first interlayer dielectric layer. A second interlayer dielectric layer is disposed at a second height over the semiconductor substrate and comprises a first dielectric material. An upper metal line is disposed at a third height over the semiconductor substrate. A via is disposed at the second height. The via extends between the lower metal line and the upper metal line. A protective dielectric structure is disposed at the second height. The protective dielectric structure comprises a protective dielectric material and is disposed along a first set of opposing sidewalls of the via, the protective dielectric material differing from the first dielectric material.

公开(公告)号：US20210193513A1

公开(公告)日：2021-06-24

申请号：US17012427

申请日：2020-09-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsi-Wen Tien ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC: H01L21/768 ,  H01L23/522

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a lower conductive structure arranged over a substrate. An etch stop layer is arranged over the lower conductive structure, and a first interconnect dielectric layer is arranged over the etch stop layer. The integrated chip further includes an interconnect via that extends through the first interconnect dielectric layer and the etch stop layer to directly contact the lower conductive structure. A protective layer surrounds outermost sidewalls of the interconnect via.