公开(公告)号：US20240339396A1

公开(公告)日：2024-10-10

申请号：US18745773

申请日：2024-06-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chieh-Han Wu ,  Cheng-Hsiung Tsai ,  Chih Wei Lu ,  Chung-Ju Lee

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/7685 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L24/32 ,  H01L24/37 ,  H01L2924/181

摘要： Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.

公开(公告)号：US12046551B2

公开(公告)日：2024-07-23

申请号：US18301447

申请日：2023-04-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chieh-Han Wu ,  Cheng-Hsiung Tsai ,  Chih Wei Lu ,  Chung-Ju Lee

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/7685 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L24/32 ,  H01L24/37 ,  H01L2924/181

摘要： Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.

公开(公告)号：US11856866B2

公开(公告)日：2023-12-26

申请号：US17740145

申请日：2022-05-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hsi-Wen Tien ,  Wei-Hao Liao ,  Pin-Ren Dai ,  Chih-Wei Lu ,  Chung-Ju Lee

IPC分类号： H10N50/10 ,  G11C11/16 ,  H01L23/522 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC分类号： H10N50/10 ,  G11C11/161 ,  H01L23/5226 ,  H10B61/00 ,  H10B61/22 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

摘要： A device includes a semiconductor substrate, a bottom conductive line, a bottom electrode, a magnetic tunneling junction (MTJ), and a residue. The bottom conductive line is over the semiconductor substrate. The bottom electrode is over the bottom conductive line. The MTJ is over the bottom electrode. The residue of the MTJ is on the sidewall of the bottom electrode and is spaced apart from the bottom conductive line.

公开(公告)号：US11652054B2

公开(公告)日：2023-05-16

申请号：US17236234

申请日：2021-04-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Chieh Yao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC分类号： H01L23/535 ,  H01L21/768

CPC分类号： H01L23/535 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76895

摘要： In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a dielectric on wire structure is arranged directly over the interconnect wire. Outer sidewalls of the dielectric on wire structure are surrounded by the first interconnect dielectric layer. The integrated chip further includes a second interconnect dielectric layer arranged over the first interconnect dielectric layer, and an interconnect via that extends through the second interconnect dielectric layer and the dielectric on wire structure to contact the interconnect wire.

公开(公告)号：US11569096B2

公开(公告)日：2023-01-31

申请号：US17327580

申请日：2021-05-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hsi-Wen Tien ,  Wei-Hao Liao ,  Chih-Wei Lu ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC分类号： H01L21/48 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

摘要： An semiconductor device includes a first dielectric layer, an etch stop layer, an interconnect structure, and a second dielectric layer. The etch stop layer is over the first dielectric layer. The interconnect structure includes a conductive via in the first dielectric layer and the etch stop layer, a conductive line over the conductive via, an intermediate conductive layer over the conductive line, and a conductive pillar over the intermediate conductive layer. The interconnect structure is electrically conductive at least from a top of the conductive pillar to a bottom of the conductive via. The second dielectric layer surrounds the conductive line, the intermediate conductive layer, and the conductive pillar, wherein a bottom of the second dielectric layer is lower than a top of the conductive line, and a top of the second dielectric layer is higher than the top of the conductive line.

公开(公告)号：US10964888B2

公开(公告)日：2021-03-30

申请号：US16840100

申请日：2020-04-03

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Pin-Ren Dai ,  Chung-Ju Lee ,  Chung-Te Lin ,  Chih-Wei Lu ,  Hsi-Wen Tien ,  Tai-Yen Peng ,  Chien-Min Lee ,  Wei-Hao Liao

IPC分类号： H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

摘要： The present disclosure describes a method utilizing an ion beam etch process, instead of a RIE etch process, to form magnetic tunnel junction (MTJ) structures. For example, the method includes forming MTJ structure layers on an interconnect layer, where the interconnect layer includes a first area and a second area. The method further includes depositing a mask layer over the MTJ structure layers in the first area and forming masking structures over the MTJ structure layers in the second area. The method also includes etching with an ion beam etch process, the MTJ structure layers between the masking structures to form MTJ structures over vias in the second area of the interconnect layer; and removing, with the ion beam etch process, the mask layer, the top electrode, the MTJ stack, and a portion of the bottom electrode in the first area of the interconnect layer.

公开(公告)号：US10354954B2

公开(公告)日：2019-07-16

申请号：US16017039

申请日：2018-06-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

IPC分类号： H01L21/00 ,  H01L23/528 ,  H01L23/538 ,  H01L23/532 ,  H01L21/768 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/3213 ,  H01L23/522

摘要： The present disclosure, in some embodiments, relates to an interconnect structure. The interconnect structure has a metal body disposed over a substrate, and a metal projection protruding outward from an upper surface of the metal body. A dielectric layer is disposed over the substrate and surrounds the metal body and the metal projection. A barrier layer separates the metal body and the metal projection from the dielectric layer.

公开(公告)号：US10020259B2

公开(公告)日：2018-07-10

申请号：US15463617

申请日：2017-03-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

IPC分类号： H01L21/00 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L21/3213 ,  H01L21/3105

CPC分类号： H01L23/5283 ,  H01L21/31053 ,  H01L21/32139 ,  H01L21/7682 ,  H01L21/76852 ,  H01L21/76885 ,  H01L21/76892 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/5384 ,  H01L23/5386 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure relates to a method for forming an interconnect structure. In some embodiments, the method may be performed by forming an opening within a sacrificial layer. The sacrificial layer is over a substrate. A conductive material is formed within the opening and over the sacrificial layer. The conductive material within the opening defines a conductive body. The conductive material is patterned to define a conductive projection extending outward from the conductive body. The sacrificial layer is removed and a dielectric material is formed surrounding the conductive body and the conductive projection.

公开(公告)号：US20180033684A1

公开(公告)日：2018-02-01

申请号：US15726590

申请日：2017-10-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Sunil Kumar Singh ,  Chung-Ju Lee ,  Tien-I Bao

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/48 ,  H01L23/532

CPC分类号： H01L21/76807 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1026 ,  H01L2221/1031 ,  H01L2221/1036 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： Some embodiments relate to a semiconductor device manufacturing process. In the process, a substrate is provided, and a sacrificial layer is formed over the substrate. An opening is patterned through the sacrificial layer, and the opening is filled with conductive material. The sacrificial layer is removed while the conductive material is left in place. A first dielectric layer is formed along sidewalls of the conductive material that was left in place.

公开(公告)号：US20140131872A1

公开(公告)日：2014-05-15

申请号：US13676260

申请日：2012-11-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chih-Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

IPC分类号： H01L23/538 ,  H01L21/48

CPC分类号： H01L23/5384 ,  H01L21/486 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure is directed to a method of manufacturing an interconnect structure in which a sacrificial layer is formed over a semiconductor substrate followed by etching of the sacrificial layer to form a first feature. The metal layer is patterned and etched to form a second feature, followed by deposition of a low-k dielectric material. The method allows for formation of an interconnect structure without encountering the various problems presented by porous low-k dielectric damage.

摘要翻译： 本公开涉及一种制造互连结构的方法，其中牺牲层形成在半导体衬底上，随后蚀刻牺牲层以形成第一特征。 金属层被图案化和蚀刻以形成第二特征，随后沉积低k电介质材料。 该方法允许形成互连结构，而不会遇到由多孔低k电介质损伤所呈现的各种问题。