-
公开(公告)号：US20160254225A1
公开(公告)日：2016-09-01
申请号：US15153967
申请日：2016-05-13
发明人： Chih-Wei Lu , Chung-Ju Lee , Hsiang-Huan Lee , Tien-I Bao
IPC分类号： H01L23/538 , H01L29/06 , H01L23/532
CPC分类号： H01L23/5283 , H01L21/31053 , H01L21/32139 , H01L21/7682 , H01L21/76852 , H01L21/76885 , H01L21/76892 , H01L23/5222 , H01L23/5226 , H01L23/53214 , H01L23/53223 , H01L23/53228 , H01L23/53233 , H01L23/53238 , H01L23/53257 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L23/5384 , H01L23/5386 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure is directed to an integrated circuit. The integrated circuit has a conductive body disposed over a substrate. The conductive body has tapered sidewalls that cause an upper surface of the conductive body to have a greater width than a lower surface of the conductive body. The integrated circuit also has a projection disposed over the conductive body. The projection has tapered sidewalls that cause a lower surface of the projection to have a greater width than an upper surface of the projection and a smaller width than an upper surface of the conductive body. A dielectric material surrounds the conductive body and the projection.
摘要翻译： 本公开涉及集成电路。 集成电路具有设置在衬底上的导电体。 导电体具有锥形侧壁，其导致导电体的上表面具有比导电体的下表面更大的宽度。 集成电路还具有设置在导电体上的突起。 突起具有锥形侧壁，其使得突出部的下表面具有比突起的上表面更大的宽度，并且具有比导电体的上表面更小的宽度。 电介质材料围绕导电体和突起。
-
公开(公告)号：US09373586B2
公开(公告)日：2016-06-21
申请号：US14218060
申请日：2014-03-18
发明人： Chih-Wei Lu , Chung-Ju Lee , Hsiang-Huan Lee , Tien-I Bao
IPC分类号： H01L23/48 , H01L23/538 , H01L23/528 , H01L23/532 , H01L21/768 , H01L23/522
CPC分类号： H01L23/5283 , H01L21/31053 , H01L21/32139 , H01L21/7682 , H01L21/76852 , H01L21/76885 , H01L21/76892 , H01L23/5222 , H01L23/5226 , H01L23/53214 , H01L23/53223 , H01L23/53228 , H01L23/53233 , H01L23/53238 , H01L23/53257 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L23/5384 , H01L23/5386 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure is directed to an interconnect structure. The metal interconnect structure has a metal body disposed over a semiconductor substrate and a projection extending from the metal body. A barrier layer continuously extends over the projection from a first sidewall of metal body to an opposing second sidewall of the metal body. A layer of dielectric material is disposed over the semiconductor substrate at a position abutting the metal body and the projection.
摘要翻译： 本公开涉及互连结构。 金属互连结构具有设置在半导体衬底上的金属体和从金属体延伸的突起。 阻挡层从金属体的第一侧壁延伸到金属体的相对的第二侧壁的突起上。 电介质材料层设置在与金属体和突起物抵接的位置上的半导体衬底之上。
-
公开(公告)号：US09343356B2
公开(公告)日：2016-05-17
申请号：US13771175
申请日：2013-02-20
发明人： Chi-Liang Kuo , Tz-Jun Kuo , Hsiang-Huan Lee
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/532
CPC分类号： H01L21/76832 , H01L21/76829 , H01L21/76831 , H01L21/76834 , H01L21/76843 , H01L21/76849 , H01L21/76867 , H01L21/76885 , H01L21/76897 , H01L23/53233 , H01L23/53238 , H01L23/53266 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates to a method of forming a back-end-of-the-line metal interconnect layer. The method is performed by depositing one or more self-assembled monolayers on a semiconductor substrate to define a metal interconnect layer area. A metal interconnect layer having a plurality of metal structures is formed on the semiconductor substrate within the metal interconnect layer area. An inter-level dielectric layer is then formed onto the surface of the semiconductor substrate in areas between the plurality of metal structures.
摘要翻译： 本公开涉及一种形成后端金属互连层的方法。 该方法通过在半导体衬底上沉积一个或多个自组装单层来限定金属互连层区域来进行。 在金属互连层区域内的半导体衬底上形成具有多个金属结构的金属互连层。 然后在多个金属结构之间的区域中在半导体衬底的表面上形成层间电介质层。
-
公开(公告)号：US20140225261A1
公开(公告)日：2014-08-14
申请号：US14258175
申请日：2014-04-22
发明人： Ming Han Lee , Hai-Ching Chen , Hsiang-Huan Lee , Tien-I Bao , Chi-Lin Teng
IPC分类号： H01L23/485 , H01L23/482
CPC分类号： H01L23/4827 , H01L21/76807 , H01L21/76834 , H01L21/76843 , H01L21/76852 , H01L21/76867 , H01L21/76885 , H01L21/76897 , H01L23/528 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments of the present disclosure relate to an interconnect structure for connecting devices of a semiconductor substrate. The interconnect structure includes a dielectric layer over the substrate and a continuous conductive body passing through the dielectric layer. The continuous conductive body is made up of a lower body region and an upper body region. The lower body region has a first width defined between opposing lower sidewalls of the continuous conductive body, and the upper body region has a second width defined between opposing upper sidewalls of the continuous conductive body. The second width is less than the first width. A barrier layer separates the continuous conductive body from the dielectric layer.
摘要翻译： 本公开的一些实施例涉及用于连接半导体衬底的器件的互连结构。 所述互连结构包括在所述衬底上的电介质层和穿过所述电介质层的连续导电体。 连续导电体由下体区域和上体区域构成。 下体区域具有限定在连续导电体的相对的下侧壁之间的第一宽度，并且上体区域具有限定在连续导电体的相对的上侧壁之间的第二宽度。 第二宽度小于第一宽度。 阻挡层将连续导电体与电介质层分开。
-
公开(公告)号：US20140197538A1
公开(公告)日：2014-07-17
申请号：US14218060
申请日：2014-03-18
发明人： Chih-Wei Lu , Chung-Ju Lee , Hsiang-Huan Lee , Tien-I Bao
IPC分类号： H01L23/532 , H01L23/538
CPC分类号： H01L23/5283 , H01L21/31053 , H01L21/32139 , H01L21/7682 , H01L21/76852 , H01L21/76885 , H01L21/76892 , H01L23/5222 , H01L23/5226 , H01L23/53214 , H01L23/53223 , H01L23/53228 , H01L23/53233 , H01L23/53238 , H01L23/53257 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L23/5384 , H01L23/5386 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure is directed to an interconnect structure. The metal interconnect structure has a metal body disposed over a semiconductor substrate and a projection extending from the metal body. A barrier layer continuously extends over the projection from a first sidewall of metal body to an opposing second sidewall of the metal body. A layer of dielectric material is disposed over the semiconductor substrate at a position abutting the metal body and the projection.
摘要翻译： 本公开涉及互连结构。 金属互连结构具有设置在半导体衬底上的金属体和从金属体延伸的突起。 阻挡层从金属体的第一侧壁延伸到金属体的相对的第二侧壁的突起上。 电介质材料层设置在与金属体和突起物抵接的位置上的半导体衬底之上。
-
公开(公告)号：US08728936B1
公开(公告)日：2014-05-20
申请号：US13676260
申请日：2012-11-14
发明人： Chih-Wei Lu , Chung-Ju Lee , Hsiang-Huan Lee , Tien-I Bao
IPC分类号： H01L21/44
CPC分类号： H01L23/5384 , H01L21/486 , H01L21/7682 , H01L21/76885 , H01L23/53223 , H01L23/53233 , H01L23/53238 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure is directed to a method of manufacturing an interconnect structure in which a sacrificial layer is formed over a semiconductor substrate followed by etching of the sacrificial layer to form a first feature. The metal layer is patterned and etched to form a second feature, followed by deposition of a low-k dielectric material. The method allows for formation of an interconnect structure without encountering the various problems presented by porous low-k dielectric damage.
摘要翻译： 本公开涉及一种制造互连结构的方法，其中牺牲层形成在半导体衬底上，随后蚀刻牺牲层以形成第一特征。 金属层被图案化和蚀刻以形成第二特征，随后沉积低k电介质材料。 该方法允许形成互连结构，而不会遇到由多孔低k电介质损伤所呈现的各种问题。
-
公开(公告)号：US20170194258A1
公开(公告)日：2017-07-06
申请号：US15463617
申请日：2017-03-20
发明人： Chih-Wei Lu , Chung-Ju Lee , Hsiang-Huan Lee , Tien-I Bao
IPC分类号： H01L23/528 , H01L21/3105 , H01L23/522 , H01L21/3213 , H01L21/768 , H01L23/532
CPC分类号： H01L23/5283 , H01L21/31053 , H01L21/32139 , H01L21/7682 , H01L21/76852 , H01L21/76885 , H01L21/76892 , H01L23/5222 , H01L23/5226 , H01L23/53214 , H01L23/53223 , H01L23/53228 , H01L23/53233 , H01L23/53238 , H01L23/53257 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L23/5384 , H01L23/5386 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates to a method for forming an interconnect structure. In some embodiments, the method may be performed by forming an opening within a sacrificial layer. The sacrificial layer is over a substrate. A conductive material is formed within the opening and over the sacrificial layer. The conductive material within the opening defines a conductive body. The conductive material is patterned to define a conductive projection extending outward from the conductive body. The sacrificial layer is removed and a dielectric material is formed surrounding the conductive body and the conductive projection.
-
公开(公告)号：US09281263B2
公开(公告)日：2016-03-08
申请号：US14258175
申请日：2014-04-22
发明人： Ming Han Lee , Hai-Ching Chen , Hsiang-Huan Lee , Tien-I Bao , Chi-Lin Teng
IPC分类号： H01L23/48 , H01L23/482 , H01L21/768 , H01L23/532 , H01L23/528
CPC分类号： H01L23/4827 , H01L21/76807 , H01L21/76834 , H01L21/76843 , H01L21/76852 , H01L21/76867 , H01L21/76885 , H01L21/76897 , H01L23/528 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments of the present disclosure relate to an interconnect structure for connecting devices of a semiconductor substrate. The interconnect structure includes a dielectric layer over the substrate and a continuous conductive body passing through the dielectric layer. The continuous conductive body is made up of a lower body region and an upper body region. The lower body region has a first width defined between opposing lower sidewalls of the continuous conductive body, and the upper body region has a second width defined between opposing upper sidewalls of the continuous conductive body. The second width is less than the first width. A barrier layer separates the continuous conductive body from the dielectric layer.
摘要翻译： 本公开的一些实施例涉及用于连接半导体衬底的器件的互连结构。 所述互连结构包括在所述衬底上的电介质层和穿过所述电介质层的连续导电体。 连续导电体由下体区域和上体区域构成。 下体区域具有限定在连续导电体的相对的下侧壁之间的第一宽度，并且上体区域具有限定在连续导电体的相对的上侧壁之间的第二宽度。 第二宽度小于第一宽度。 阻挡层将连续导电体与电介质层分开。
-
公开(公告)号：US20150255334A1
公开(公告)日：2015-09-10
申请号：US14720264
申请日：2015-05-22
发明人： Shin-Yi Yang , Ching-Fu Yeh , Tz-Jun Kuo , Hsiang-Huan Lee , Ming-Han Lee
IPC分类号： H01L21/768
CPC分类号： H01L21/76873 , C25D3/38 , C25D7/123 , H01L21/288 , H01L21/2885 , H01L21/44 , H01L21/76802 , H01L21/76843 , H01L21/76861 , H01L21/76871 , H01L21/76877 , H01L21/76879
摘要： Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a conductive layer deposited on the seed layer in a single plating process step by applying a plating solution in the via/trench opening.
摘要翻译： 这里提出的是一种电镀方法，包括提供一个具有形成在一个迹线上的电介质层的衬底，以及形成延伸穿过该电介质层的通孔/沟槽开口，该通孔/沟槽开口暴露该迹线的表面。 该方法还包括在通孔/沟槽开口中形成种子层并与迹线接触并在种子层上形成保护层。 去除保护层，并通过在通孔/沟槽开口中施加电镀溶液，在单个电镀工艺步骤中在种子层上沉积导电层。
-
公开(公告)号：US20240153870A1
公开(公告)日：2024-05-09
申请号：US18413426
申请日：2024-01-16
发明人： Chao-Hsien Peng , Hsiang-Huan Lee , Shau-Lin Shue
IPC分类号： H01L23/522 , H01L21/285 , H01L21/3213 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/28556 , H01L21/32139 , H01L21/76879 , H01L21/76885 , H01L23/53238
摘要： A method includes etching a mandrel layer to form mandrel strips, and selectively depositing metal lines on sidewalls of the mandrel strips. During the selective deposition, top surfaces of the mandrel strips are masked by dielectric masks. The method further includes removing the mandrel layer and the dielectric masks, filling spaces between the metal lines with a dielectric material, forming via openings in the dielectric material, with top surfaces of the metal lines exposed to the via openings, and filling the via openings with a conductive material to form vias.
-
-
-
-
-
-
-
-
-
搜索结果
22 条记录 (耗时 0.018 秒)
