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1.发明申请公开(公告)号：US20170316138A1
公开(公告)日：2017-11-02
申请号：US15335091
申请日：2016-10-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Katherine Chiang , Cheng Hsiao , Chang-Yu Huang , Juan Yi Chen , Ke-Wei Su , Chung-Kai Lin , Lester Chang , Min-Chie Jeng
Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.
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2.发明授权Analytical model for predicting current mismatch in metal oxide semiconductor arrays 有权用于预测金属氧化物半导体阵列中的电流失配的分析模型公开(公告)号：US09378314B2
公开(公告)日：2016-06-28
申请号：US14467327
申请日：2014-08-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Amit Kundu , Jaw-Juinn Horng , Yung-Chow Peng , Shih-Cheng Yang , Chung-Kai Lin
CPC classification number: G06F17/5036 , G06F17/5072 , G06F2217/10 , G06F2217/78 , H01L27/0207
Abstract: A system and method for designing integrated circuits and predicting current mismatch in a metal oxide semiconductor (MOS) array. A first subset of cells in the MOS array is selected and current measured for each of these cells. Standard deviation of current for each cell in the first subset of cells is determined with respect to current of a reference cell. Standard deviation of local variation can be determined using the determined standard deviation of current for one or more cells in the first subset. Standard deviations of variation induced by, for example, poly density gradient effects, in the x and/or y direction of the array can then be determined and current mismatch for any cell in the array determined therefrom.
Abstract translation: 一种用于设计集成电路并预测金属氧化物半导体（MOS）阵列中的电流失配的系统和方法。 选择MOS阵列中的单元的第一子集，并且对这些单元中的每一个进行电流测量。 相对于参考单元的电流确定单元的第一子集中的每个单元的电流的标准偏差。 可以使用确定的第一子集中的一个或多个单元的电流的标准偏差来确定局部变化的标准偏差。 然后可以确定由阵列的x和/或y方向由例如多晶密度梯度效应引起的变化的标准偏差，并且由阵列确定阵列中的任何单元的电流失配。
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Patent Agency Ranking
3.发明授权Analytical model for predicting current mismatch in metal oxide semiconductor arrays 有权用于预测金属氧化物半导体阵列中的电流失配的分析模型公开(公告)号：US08832619B2
公开(公告)日：2014-09-09
申请号：US13751195
申请日：2013-01-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Amit Kundu , Jaw-Juinn Horng , Yung-Chow Peng , Shih-Cheng Yang , Chung-Kai Lin
CPC classification number: G06F17/5036 , G06F17/5072 , G06F2217/10 , G06F2217/78 , H01L27/0207
Abstract: A system and method for designing integrated circuits and predicting current mismatch in a metal oxide semiconductor (MOS) array. A first subset of cells in the MOS array is selected and current measured for each of these cells. Standard deviation of current for each cell in the first subset of cells is determined with respect to current of a reference cell. Standard deviation of local variation can be determined using the determined standard deviation of current for one or more cells in the first subset. Standard deviations of variation induced by, for example, poly density gradient effects, in the x and/or y direction of the array can then be determined and current mismatch for any cell in the array determined therefrom.
Abstract translation: 一种用于设计集成电路并预测金属氧化物半导体（MOS）阵列中的电流失配的系统和方法。 选择MOS阵列中的单元的第一子集，并且对这些单元中的每一个进行电流测量。 相对于参考单元的电流确定单元的第一子集中的每个单元的电流的标准偏差。 可以使用确定的第一子集中的一个或多个单元的电流的标准偏差来确定局部变化的标准偏差。 然后可以确定由阵列的x和/或y方向由例如多晶密度梯度效应引起的变化的标准偏差，并且由阵列确定阵列中的任何单元的电流失配。
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4.发明授权公开(公告)号：US10860769B2
公开(公告)日：2020-12-08
申请号：US16721255
申请日：2019-12-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Katherine Chiang , Cheng Hsiao , Chang-Yu Huang , Juan Yi Chen , Ke-Wei Su , Chung-Kai Lin , Lester Chang , Min-Chie Jeng
IPC: G06F30/39 , G06F30/367 , G06F7/58
Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.
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5.发明授权公开(公告)号：US10521538B2
公开(公告)日：2019-12-31
申请号：US15335091
申请日：2016-10-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Katherine Chiang , Cheng Hsiao , Chang-Yu Huang , Juan Yi Chen , Ke-Wei Su , Chung-Kai Lin , Lester Chang , Min-Chie Jeng
Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.
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6.发明申请公开(公告)号：US20200125782A1
公开(公告)日：2020-04-23
申请号：US16721255
申请日：2019-12-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Katherine Chiang , Cheng Hsiao , Chang-Yu Huang , Juan Yi Chen , Ke-Wei Su , Chung-Kai Lin , Lester Chang , Min-Chie Jeng
IPC: G06F30/39 , G06F7/58 , G06F30/367
Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.
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7.发明授权公开(公告)号：US10216879B1
公开(公告)日：2019-02-26
申请号：US15682863
申请日：2017-08-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Shun Huang , Wai-Kit Lee , Ya-Chin Liang , Cheng Hsiao , Juan-Yi Chen , Li-Chung Hsu , Ting-Sheng Huang , Ke-Wei Su , Chung-Kai Lin , Min-Chie Jeng
Abstract: A method for establishing an aging model of a device is provided. The device is measured to obtain degradation information of the device under an operating condition, wherein the device is a physical device. The degradation information is partitioned into a permanent degradation portion and an impermanent degradation portion. The impermanent degradation portion is differentiated by time to obtain a differential value. The aging model is obtained according to the differential value. When the differential value is greater than zero, a degradation of the device increases over time, and when the differential value is less than zero, the degradation of the device decreases over time.
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